Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2011-04-12
2011-04-12
Tabone, Jr., John J (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S727000, C714S729000, C716S030000, C703S014000, C703S022000, C324S765010
Reexamination Certificate
active
07925940
ABSTRACT:
A computer is programmed to prepare a computer program for simulating operation of an integrated circuit (IC) chip, in order to test scan circuitry therein. The computer is programmed to trace a path through combinational logic in a design of the IC chip, starting from an output port of a first scan cell and ending in an input port of a second scan cell. If the first and second scan cells receive a common scan enable signal, then the computer generates at least a portion of the computer program, i.e. software to perform simulation of propagating a signal through the path conditionally, for example when the common scan enable signal is inactive and alternatively to skip performing simulation when the common scan enable signal is active. The computer stores the portion of the computer program in memory, for use with other such portions of the computer program.
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Jain Manish
Pandey Yogesh
Sankar Vijay Anand
Evergreen Valley Law Group P.C.
Radhakrishnan Kanika
Synopsys Inc.
Tabone, Jr. John J
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