Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2011-05-03
2011-05-03
Tran, Minh-Loan T (Department: 2826)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C257SE21424
Reexamination Certificate
active
07935588
ABSTRACT:
NFET and PFET devices with separately strained channel regions, and methods of their fabrication is disclosed. A stressing layer overlays the device in a manner that the stressing layer is non-conformal with respect the gate. The non-conformality of the stressing layer increases the amount of stress that is imparted onto the channel of the device, in comparison to stressing layers which are conformal. The method for overlaying in a non-conformal manner includes non-conformal deposition techniques, as well as, conformal depositions where subsequently the layer is turned into a non-conformal one by etching.
REFERENCES:
patent: 6977194 (2005-12-01), Belyansky
patent: 7002209 (2006-02-01), Chen
patent: 7105394 (2006-09-01), Hachimine
patent: 7115954 (2006-10-01), Shimizu
patent: 7205615 (2007-04-01), Tsutsui
patent: 7223647 (2007-05-01), Hsu
patent: 2005/0158955 (2005-07-01), Yang et al.
patent: 2006/0057787 (2006-03-01), Doris
patent: 2006/0249794 (2006-11-01), Teh et al.
patent: 2007/0077765 (2007-04-01), Prince et al.
patent: 2007/0096220 (2007-05-01), Kim et al.
“High speed 45 nm gate length CMOSFETs integrated into a 90nm bulk technology incorporating strain engineering” V. Chan et al., IEDM Tech. Dig., pp. 77-80, 2003.
“Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing” H..S. Yang, et al., IEDM Tech. Dig., pp. 1075-1078, 2004.
Doris Bruce B.
Liu Xiao Hu
International Business Machines - Corporation
Percello Louis J.
Quinto Kevin
Sai-Halasz George
Tran Minh-Loan T
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