Enhanced transistor performance by non-conformal stressed...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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C257SE21424

Reexamination Certificate

active

07935588

ABSTRACT:
NFET and PFET devices with separately strained channel regions, and methods of their fabrication is disclosed. A stressing layer overlays the device in a manner that the stressing layer is non-conformal with respect the gate. The non-conformality of the stressing layer increases the amount of stress that is imparted onto the channel of the device, in comparison to stressing layers which are conformal. The method for overlaying in a non-conformal manner includes non-conformal deposition techniques, as well as, conformal depositions where subsequently the layer is turned into a non-conformal one by etching.

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“Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing” H..S. Yang, et al., IEDM Tech. Dig., pp. 1075-1078, 2004.

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