Semiconductor device manufacturing: process – Radiation or energy treatment modifying properties of...
Reexamination Certificate
2001-12-14
2004-12-07
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Radiation or energy treatment modifying properties of...
C438S671000, C438S720000, C438S723000, C438S719000, C430S328000, C430S313000, C430S296000
Reexamination Certificate
active
06828259
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to integrated circuit (IC) fabrication. More particularly, the present invention relates to fabrication of transistors having uniform gate widths, reduced gate widths, and preserved minimum extension of the gates onto the field isolation region.
BACKGROUND OF THE INVENTION
The semiconductor or integrated circuit (IC) industry aims to manufacture ICs with higher and higher densities of devices on a smaller chip area to achieve greater functionality and to reduce manufacturing costs. This desire for large scale integration requires continued shrinking of circuit dimensions and device features. The ability to reduce the size of structures, such as, gate lengths and widths in field-effect transistors or the width of conductive lines, is driven by the performance of lithographic tools (e.g., wavelength of the exposure sources), resolution enhancement techniques (e.g., phase shifting masks, off-axis illumination, etc.), and photoresist materials (collectively referred to as lithographic techniques).
However, currently available lithographic techniques lack the resolution to print sufficiently small IC device features. Thus, various non-lithographic techniques are also employed to shrink or reduce feature dimensions after lithographic printing. One such non-lithographic technique is a resist trimming process that reduces or “trims” features patterned on a photoresist layer of a semiconductor wafer before such features are transferred to the underlying layer(s) of the semiconductor wafer. The resist trimming process utilizes a plasma etch to remove the desired amount of the patterned photoresist material. As an example, a feature patterned on a polystyrene-based photoresist material typically employed for wafer patterning using a 248 nm wavelength of light lithography process can initially have a dimension on the order of 150 nm and be plasma trimmed to a dimension of approximately 100 nm or less.
In contrast, it is difficult for features patterned on an acrylic, cycloacrilate and cycloolephine polymer-based photoresist material typically employed in lithography processes using 193 nm wavelength of light to realize a similar amount of dimensional reduction from a resist trimming process.
Present photoresist material used for 193 nm lithography exhibits poor trimming properties, suffering from, among other problems, high vertical resist erosion rate (Rv), low horizontal trim rate (Rh), a high rate of erosion of the ends of lines (Re). When attempting to trim resist to the small gate dimensions required for modern VLSI transistors, it is quite common for the vertical erosion rate to completely consume portions of the resist pattern before the desired in-plane dimensions have been reached, resulting in damaged or discontinuous transistor gates or gates exhibiting an unacceptably high and variable series resistance.
A typical resist material used in 193 nm lithography exhibits poor trimming properties, suffering from, among others, uncontrollable and different trim rates in the horizontal and vertical directions. It is not uncommon for features patterned on 193 nm photoresist materials to become deformed and/or consumed in the course of the resist trimming process, thereby preventing subsequent processes from commencing.
For example, transistor gates patterned using 193 nm lithography and a typical commercially available photoresist material can have critical dimensions (CDs) of 130-110 nm before the resist trimming process and the final critical dimensions (CDs) of approximately 70-80 nm after the resist trimming process. Any further trimming would typically result in non-uniform widths along the length of the gates, unacceptable consumption of the minimum extension of the gates onto the field isolation regions, (i.e. unacceptably large end of the line pull back) and/or excessive thinning of the gate pattern over topography steps such that pattern transfer to the underlying layer(s) of the wafer is not possible. Such poor trimming results can affect the operating conditions and/or performance of the transistors to the extent that the resist trimming process will become unusable without violating design rules for given technology scaling requirements.
Thus, there is a need for a process for enhancing the resist trimmability during etch and resist stability during etch to enable the successful transfer of transistor gates patterned on photoresist materials. There is a further need for a process of fabricating transistor gates having smaller critical dimensions, uniform widths along its length, and/or preserved minimum extension of the gates onto the field isolation regions than is possible with conventional photolithography and resist trimming process.
SUMMARY OF THE INVENTION
One embodiment of the invention relates to an integrated circuit fabrication process. The process includes patterning a transistor gate pattern on a photoresist layer, and curing the transistor gate pattern with an electron beam. The process further includes trimming the cured transistor gate pattern, and transferring the trimmed transistor gate pattern to a layer disposed below the photoresist layer to form a transistor gate. The transistor gate includes a width and a length. A variation of the width along the length of the transistor gate is reduced due to the curing step.
Another embodiment of the invention relates to a method of forming a transistor having a gate width of less than 70 nm. The method includes E-beam irradiation of a gate pattern of a photoresist layer, and trimming the E-beam irradiated gate pattern of the photoresist layer. The method further includes etching a polysilicon layer disposed below the photoresist layer in accordance with the trimmed gate pattern to form a gate of the transistor. The gate width is preferably less than 70 nm.
Still another embodiment of the invention relates to an integrated circuit. The integrated circuit includes an isolation region and a transistor surrounded by the isolation region. The transistor includes a gate. A critical dimension of the gate is less than approximately 60 nm. The gate is defined by an E-beam irradiated gate feature on a photoresist layer and trimming the E-beam radiation irradiated gate pattern of the photoresist layer, while preserving the gate to isolation line extension to ensure enhanced transistor performance.
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Callahan Russell R.A.
Fisher Philip A.
Khathuria Ashok M.
Plat Marina V.
Yang Chih-Yuh
Foley & Lardner LLP
Maldonado Julio J.
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