Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1998-03-13
2000-06-13
Bowers, Charles
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438648, H01L 21336
Patent
active
060749229
ABSTRACT:
A method for increasing salicide thickness and effective polysilicon width at a narrow polysilicon line while reducing resistance and reducing source/drain bridging risk in the fabrication of a silicided polysilicon gate is described. A polysilicon layer is provided overlying a gate oxide layer on a semiconductor substrate. A dielectric layer, such as silicon oxide, is deposited overlying the polysilicon layer. The silicon oxide layer, polysilicon layer, and gate oxide layer are patterned to form a polysilicon gate electrode having a silicon oxide layer on top of the gate electrode. Dielectric spacers, such as silicon nitride, are formed on the sidewalls of the gate electrode and the silicon oxide layer. In an alternative, silicon spacers may be formed between the gate and the silicon nitride spacers to increase the effective width of the polysilicon line. Source and drain regions associated with the gate electrode are formed within the semiconductor substrate. The silicon oxide layer on top of gate electrode is removed whereby the silicon nitride spacers extend above the gate electrode. A metal silicide is formed on the top surface of the gate electrode and over the source and drain regions. The dielectric spacers extending higher than the gate electrode prevent source/drain bridging during silicidation. This completes the formation of the salicided polysilicon gate electrode.
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Hsu Jung-Hsien
Wang Pi-Shan
Weng Chun-Wen
Ackerman Stephen B.
Bowers Charles
Hawranek Scott J.
Pike Rosemary L.S.
Saile George O.
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