Enhanced silicidation formation for high speed MOS device by jun

Details Enhanced silicidation formation for high speed MOS device by jun Enhanced silicidation formation for high speed MOS device by jun

1998-11-25

2000-12-26

Pham, Long

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438307, 438526, 438682, H01L 21336

Patent

active

061658588

ABSTRACT:
A method of making a MOS transistors in an integrated circuit includes forming a plurality of doped source and drain regions adjacent respective gate structures that include gate dielectrics, gate conductors and spacers. The plurality of doped source and drain regions are formed at different depths, at different doses and with differing dopants. In one embodiment, first doped source and drain regions are formed at a first depth, at a first dose using a first dopant while second doped source and drain regions are formed at a second depth, at a second dose using a second dopant. The first depth is shallower than the second depth so that the first doped source and drain regions serve as sacrificial doped regions that are consumed in a silicidation process when they are converted into a silicide by being combined with a silicidation metal. However, the second doped source and drain regions maintain their doping profiles and dopant levels. The implant energy of the dopants depends upon their molecular weight and desired doping depths. The dose of such doping depends upon desired drive current and other characteristics of the transistors.

REFERENCES:
patent: 5607884 (1997-03-01), Wu
patent: 5770507 (1998-06-01), Chen et al.
patent: 5780347 (1998-07-01), Kapoor
patent: 5891785 (1999-04-01), Chang
patent: 6001676 (1999-12-01), Sawada et al.
patent: 6025241 (2000-02-01), Lin et al.

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