Enhanced side-wall stacked capacitor

Details Enhanced side-wall stacked capacitor Enhanced side-wall stacked capacitor

1998-06-18

2002-06-04

Tsai, Jey (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S255000

Reexamination Certificate

active

06399437

ABSTRACT:

FIELD OF THE INVENTION
The present invention generally relates to a stacked capacitor for a semiconductor device and a method of making such capacitor and more particularly, relates to a stacked capacitor for a dynamic random access memory (DRAM) device that has enhanced side-wall for improved capacitance and a method of fabricating the capacitor.
BACKGROUND OF THE INVENTION
In the technology of fabricating DRAM devices for integrated circuits, it is important for a storage node capacitor cell that is built into the device to have a large capacitance in order to retain adequate voltages. In modern semiconductor devices, circuit density continues to increase since smaller chips are being made that are packed with ever-increasing number of circuits. Based on the fact that the chip real estate is limited, the only possible way of increasing the capacitance of a storage node capacitor cell is to increase it three-dimensionally, i.e. to grow the cell in the vertical dimension.
In the fabrication of modern DRAM devices, as the fabrication process grows increasingly minute, for instance, from a 0.45 &mgr;m fabrication process down to a 0.38 &mgr;m fabrication process, the chip real estate available for a storage node capacitor must be proportionally reduced. In order to maintain the same capacitance, or to obtain a higher capacitance, the dimensions of the storage node capacitor cell must be redesigned, i.e., generally to increase the height of the capacitor cell.
Using a 16 mega DRAM device as an example, when the fabrication process used is changed from 0.45 &mgr;m to 0.38 &mgr;m, the corresponding capacitance of the capacitor cell is reduced from 25 fF to 18 fF. The fabrication process for the cell must therefore be modified and the cell structure be improved in order to increase the capacitance of storage cells fabricated by the 0.38 &mgr;m process.
In the conventional 0.45 &mgr;m fabrication process, attempts have been made by others to deposit rugged polysilicon at a lower deposition temperature in order to increase the surface area of the capacitor cell. Even though the capacitor cell surface area can be increased by using rugged polysilicon at the ever-miniaturizing fabrication technology, the increased capacitance achieved by using rugged polysilicon can no longer satisfy the demand for higher capacitance.
A conventional 0.45 &mgr;m fabrication process of a storage node capacitor cell for a DRAM device is shown in
FIGS. 1-5
. Referring initially to
FIG. 1
, wherein a semiconductor substrate
10
is shown which has a layer of a non-doped silicate glass
12
deposited on top. After the insulating layer
12
is photomasked and etched in a conventional etching process, the substrate area
14
is exposed as the storage node capacitor call contact, Next, as shown in
FIG. 2
, a layer of polysilicon (Poly-2) is deposited as a conformal coating
16
. The thickness of Poly-2 is normally in the range between about 400 Å and 700 Å, even though a thickness of 500 Å is frequently used. In order to increase the surface area of the polysilicon layer, a rugged surface polysilicon layer
18
is deposited at a relatively low deposition temperature of between about 500° C. and 600° C. by a chemical vapor deposition technique. The deposition temperature of the rugged polysilicon should be kept relatively low in order to maintain the wave-like surface texture of the rugged polysilicon. It is known that at temperatures above 600° C. the wave-like textured surface of the rugged polysilicon will become smooth and therefore looses its benefit of the large surface areas. The thickness of the rugged polysilicon layer deposited is generally between about 700 Å and about 1000 Å. This is shown in FIG.
3
. In a capacitor cell that utilizes rugged polysilicon, it is therefore important not to subject the device in a down-stream process that may be operated at a temperature of higher than 600° C.
In a subsequent process, the Poly-2 layer and the rugged polysilicon layer are patterned by a photomasking process and etched to form the base of the storage node capacitor cell. This is shown in FIG.
4
. In the final fabrication step, a second insulating layer, preferably of an oxide-nitride-oxide (ONO) insulating material is deposited by a chemical vapor deposition technique. After the ONO layer
20
is patterned and etched to form a conformal layer on the capacitor cell, a final layer
22
of polysilicon (Poly-3) is deposited by a chemical vapor deposition technique and subsequently formed as the final conformal layer on the storage node capacitor. A conventionally formed storage node capacitor that incorporated the use of a rugged surface polysilicon layer is thus completed.
It is therefore an object of the present invention to provide a stacked capacitor in a DRAM device that has improved capacitance when compared to conventional capacitor cells that incorporate rugged polysilicon layers.
It is another object of the present invention to provide a stacked capacitor in a DRAM device that has improved capacitance without utilizing more chip real estate.
It is a further object of the present invention to provide a stacked capacitor in a DRAM device that has improved capacitance by utilizing the same chip real estate.
It is still another object of the present invention to provide a stacked capacitor for a DRAM device that has improved capacitance by growing three-dimensionally the height of the capacitor cell.
It is yet another object of the present invention to provide a stacked capacitor for a DRAM device that has improved capacitance by enhancing the side-wall thickness of the capacitor cell.
It is still another further object of the present invention to provide a stacked capacitor for a DRAM device that has improved capacitance due to enhanced side-wall thickness achieved by the deposition of an additional layer of polysilicon.
It is yet another further object of the present invention to provide a method of fabricating a stacked capacitor in a DRAM device that has improved capacitance by depositing an additional polysilicon layer prior to the forming of the capacitor cell contact such that the side-wall thickness of the cell can be increased.
SUMMARY OF THE INVENTION
According to the present invention, a stacked capacitor in a DRAM device that has improved capacitance is provided. In the preferred embodiment, an additional polysilicon layer is deposited prior to the formation of the capacitor cell contact such that the thickness of the side-wall is increased to improve the capacitance. The thickness of the additional polysilicon layer can be suitably determined in the range between about 1000 Å and about 6000 Å based on the specific application requirement. The thicker the polysilicon layer deposited, the higher the capacitance of the capacitor cell can be achieved.
The fabrication method of the preferred embodiment can be carried out by first providing a semiconductor substrate, blanket depositing a first insulating layer on the substrate, blanket depositing a first polysilicon layer on the first insulating layer, photomasking and etching a cell contact area for the capacitor in the first insulating and the first polysilicon layer to expose the substrate, depositing a conformal polysilicon layer on top of the first polysilicon layer and the cell contact area, depositing a conformal third polysilicon layer of rugged polysilicon layer over the second polysilicon layer, photomasking and etching the first, the second polysilicon layer and the third rugged polysilicon layer in areas other than that defining the capacitor cell, depositing a conformal second insulating layer over the third polysilicon layer, depositing a conformal fourth polysilicon layer over the second insulating layer, and then photomasking and etching the second insulating layer and the fourth polysilicon layer to define the stacked capacitor.
The preferred embodiment of the present invention further provides a stacked capacitor formed in a semiconductor device that includes a semiconductor substrate

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