Enhanced nitride layers for metal oxide semiconductors

Details Enhanced nitride layers for metal oxide semiconductors Enhanced nitride layers for metal oxide semiconductors

2008-01-01

2008-01-01

Geyer, Scott B. (Department: 2812)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Multiple layers

C438S763000, C438S791000, C257SE21002

Reexamination Certificate

active

07314836

ABSTRACT:
The performance of NMOS and PMOS regions of integrated circuits is improved. Embodiments of the invention include forming a first dielectric layer optimized for n-doped regions over the n-doped regions and forming a second dielectric layer optimized for p-doped regions over p-doped regions.

REFERENCES:
patent: 6174775 (2001-01-01), Liaw
patent: 6573172 (2003-06-01), En et al.
patent: 2003/0040158 (2003-02-01), Saitoh
patent: 2004/0104405 (2004-06-01), Huang et al.
patent: 2004/0113217 (2004-06-01), Chidambarrao et al.
patent: 2005/0230756 (2005-10-01), Chang et al.

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