Enhanced macrocell module for high density CPLD architectures

Details Enhanced macrocell module for high density CPLD architectures Enhanced macrocell module for high density CPLD architectures

1999-06-06

2000-11-21

Nelms, David

Electronic digital logic circuitry

Multifunctional or programmable

Array

326 39, H03K 19177

Patent

active

061508411

ABSTRACT:
An improved CPLD includes a plurality of macrocell modules (MM's) where each MM can receive a relatively large number of independent inputs (at least 80) and can generate at least 5 different product term signals (PT's) therefrom. All 5 PT's may be used for generating a local sum-of-products (SoP). Any of the 5 PT's may be stolen (steered-away) to instead provide a local control for its macrocell module. Each module includes a local SoS-producing gate that can produce a sums-of-sums signal (SoS) that represents a Boolean sum of one or more of the local SoP signal, of SoP signals of neighboring macrocell modules, and of SoS signals of neighboring macrocell modules. Simple allocation and super-allocation may be used to produce sums-of-sums signals of relatively large, one-pass function depth, such as 160PT's in one pass.

REFERENCES:
patent: 5883525 (1999-03-01), Tavana et al.
patent: 5894565 (1999-04-01), Furtek et al.
patent: 5952846 (1999-09-01), Silver
patent: 5966027 (1999-10-01), Kapusta et al.
Product information sheet: ispLSI 8000 Family Overview, Lattice Semiconductor Corporation, May 6, 1999, 4 pgs.
Product information sheet: ispLSI 5000V Family Overview, Lattice Semiconductor Corporation, Mar. 19, 1999, 3 pgs.
Product specification: 960 macrocell SRAM CPLD, Philips Semiconductors, Mar. 18, 1999, 2 pgs.
Product specification: 128 macrocell CPLD, Philips Semiconductors, Jul. 23, 1998, 1 pg.

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