Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Insulating material
Patent
1999-06-14
2000-12-12
Williams, Alexander O.
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Insulating material
257712, 257709, 257738, 257788, 257787, 257687, 257693, 257698, 361758, 361714, 361715, H01L 2334, H05K 503, H05K 504, H05K 720
Patent
active
061603112
ABSTRACT:
An enhanced heat dissipating Chip Scale Package (CSP) method and devices include preparing a heat dissipating base with a recess surrounded by a guarding wall. A chip with an integrated circuit (IC) layout is adhered the heat dissipating base in the recess. A substrate with a metallic circuit layer that is smaller size than the chip is then adhered to the chip. Then coupling the metallic circuit layer with the IC layout. A non-conductive resin is then filled in the recess within the guarding wall and covers the coupling portion. The resulting package device produced by means of BGA package process is small size and has enhanced heat dissipating property. The Package size/chip size ratio may be lower than 1.2 to meet the CSP requirements.
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patent: 5998241 (1999-12-01), Niwa
Chen Tsung-Chieh
Peng Yi-Liang
First International Computer Inc.
Williams Alexander O.
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