Enhanced etching/smoothing of dielectric surfaces

Details Enhanced etching/smoothing of dielectric surfaces Enhanced etching/smoothing of dielectric surfaces

2001-10-02

2003-09-23

Kunemund, Robert (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C156S345100, C118S7230CB, C315S111810

Reexamination Certificate

active

06624081

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates generally to the smoothing of dielectric surfaces, and, more particularly to the etching/smoothing of dielectric surfaces wherein it is desirable to avoid exposing such dielectric to the effects of ultraviolet radiation, X-ray radiation and/or ionizing electromagnetic radiation.
As integrated circuit device sizes have been shrunk to create denser, more functional devices, the gate delays of the devices have typically become shorter and the devices have become faster. However, the corresponding shrinking of the integrated circuits' interconnecting metal lines and of the inter-metal dielectric insulators, has resulted in increased signal propagation delays. These increasing interconnection propagation delays have generally resulted from the increased resistance of the thinner metal interconnect lines and the increased capacitance that results from closer spacing of conductors and from the thinner insulating dielectric layers which are necessitated. This situation, which is well known in the integrated circuit development community, poses a barrier to continued successful increases in integrated circuit density, speed, and functionality.
In order to continue shrinking integrated circuit devices while maintaining or improving their speeds, designers of integrated circuit interconnect are finding it necessary to reduce the resistivity of the metals used and to reduce the inter-metal (both interline and interlayer) capacitances. This trend can be noted in the developing shift from the longstanding use of aluminum interconnect metal to the use of lower resistivity copper. It can also be noted in the developing shift from the use of SiO
2
as the dielectric material of choice (having dielectric constant, k≡3.9) towards the use of dielectric materials having a lower dielectric constants (low-k materials) in the range of 3>k>1. In order for future generations of integrated circuits to meet their performance goals, the materials and methods for routine fabrication of low-k materials for inter-metal dielectric insulation must be developed. One example of an interconnecting structure which is being developed to take advantage of lower resistivity metal conductors and low-k inter-metal dielectric materials is known in the semiconductor industry as “copper dual damascene interconnect.”
Because of the critical nature of this problem for the integrated circuit manufacturing community, a very large effort is being expended to identify and develop low-k materials and methods for their incorporation into the product process flow. In addition to low dielectric constant, there are many other requirements for suitable insulating materials. These include low cost, high leakage resistance, mechanical strength, thermal stability, non-corrosiveness, compatible coefficient of expansion, ease of deposition, gap filling ability, appropriate etching characteristics, ability to act as a migration barrier, and numerous other desired characteristics. No material appears to satisfy all requirements, and so the industry is examining tradeoffs between various possible materials.
One class of low-k materials that is of considerable interest is a family of fluorine-containing polymers generally known as parylenes. These materials have been successfully applied for some time in a variety of industries where conformal dielectric coating of complex shapes has been required. At least two parylenes known as parylene-N and parylene-F have been discussed by R. S. List, et. al. in MRS Bulletin, October, 1997, p.61. They show that these parylenes have properties that are considered favorable for use as potential low-k (k<2.5) integrated circuit dielectric materials and methods have been devised (for example those taught in U.S. Pat. No. 5,879,808—Wray, et. al.) for fabricating them into the multi-level structures required separating circuit interconnection layers.
Historically, SiO
2
has been used as the primary dielectric material for silicon integrated circuits. A factor in it's longstanding utility has been the ease and precision with which it can be etched into a desired patterns and thickness using wet chemistry etchants such as hydrofluoric acid and the like. As device geometries have become smaller, there has been an increase in the use of dry etching techniques because of their tendency to be able to produce finer patterns. Most modern low-k dielectric materials including parylene have been generally understood to be best etched using dry etching methods such as plasma etching, ion etching, and the like, rather than by wet etching.
A problem exists, however, in that plasma etching and other dry etching processes are known to sometimes leave a degree of damage on and beneath the etched surfaces. Furthermore, conventional dry etching processes (plasma etching, reactive ion etching, conventional ion etching, sputter etching, and ion beam milling) all unavoidably expose the etched surface to electromagnetic radiation including ultraviolet wavelengths—because the substrate to be etched is directly exposed to radiation from the associated plasma.
Fluorine-containing polymers (fluoropolymers) such as parylene can react, upon exposure to ultraviolet of appropriate wavelengths, to liberate fluorine, which though chemically unbound may remain entrapped in the fluoropolymer matrix. Adjacent metal interconnect layers may eventually react with the corrosive free fluorine, resulting in a shortened useful lifetime of the integrated circuit. This creates a potential integrated circuit device reliability problem.
There is a need for a dry etching technique capable of efficiently producing uniformly homogeneous etching over large diameter (200-300 mm or larger) wafers without residual damage and without producing residual free fluorine in order to enable greater success in the application of fluoropolymers (such as parylenes) for use as inter-metal low-k dielectrics in future integrated circuit generations.
The concept of using gas cluster ion beams (GCIB) for dry etching, cleaning, and smoothing of hard materials is known in the art and has been described by Deguchi, et.al in U.S. Pat. No. 5,814,194. Because ionized clusters containing on the order of thousands of gas atoms or molecules may be formed and accelerated to modest energies on the order of a few thousands of electron volts, individual atoms or molecules in the clusters each only have an average energy on the order of a few electron volts. It is known from the teachings of Yamada, U.S. Pat. No. 5,459,326, that such individual atoms are not individually energetic enough to significantly penetrate a surface to cause the residual surface damage typically associated with the other types of dry etching in which individual atoms have energies on the order of hundreds or thousands of electron volts. Nevertheless, the clusters themselves are sufficiently energetic (some thousands of electron volts) to effectively etch, smooth, or clean hard surfaces.
An important consideration in the ion beam processing of surfaces covered by insulating films (as is the case when fluoropolymer films are deposited on semiconductor wafers) is the tendency for the charged beam to induce charging of the surface being processed (etched, in this case). If sufficient charge is permitted to accumulate on the insulating surface without means for dissipation, the dielectric properties of the film may be exceeded and the film can be ruptured or otherwise permanently damaged by the electrical stress. This problem is well known in ion beam processing such as ion implantation, ion milling, and GCIB processing. It is to be expected that means of limiting the surface charging of fluoropolymer films during GCIB etching must be provided if undesirable and harmful charging is to be avoided. When the positive cluster ions strike the insulating film, they may transfer their charge to the film. The collision process also results in the liberation of secondary particles from the surface—surface atoms thus liberated result in the etching of the

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