Enhanced bus turnaround integrated circuit dynamic random...

Details Enhanced bus turnaround integrated circuit dynamic random... Enhanced bus turnaround integrated circuit dynamic random...

2000-07-27

2001-10-09

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S049130, C365S195000

Reexamination Certificate

active

06301183

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates, in general, to the field of integrated circuit memory devices. More particularly, the present invention relates to an enhanced bus turnaround (EBT™ is a trademark of Enhanced Memory Systems, Inc., Colorado Springs, Col.) integrated circuit dynamic random access memory (“DRAM”) device of particular utility in providing maximum DRAM performance while concomitantly affording a device with may be readily integrated into systems designed to use zero bus turnaround (“ZBT”), or pipeline burst static random access memory (“SRAM”) devices.
ZBT is a synchronous SRAM architecture which is optimized for switching and router functions which require frequent and highly randomized Read and Write operations such as those found in typical networking and telecommunications applications. In operation, ZBT SRAM devices serve to eliminate idle clock cycles which might otherwise be encountered in accesses to a data bus which alternate often between Write and Read operations. ZBT SRAM's eliminate dead cycles and provide maximum memory bandwidth utilization. All critical timing parameters for ZBT SRAM devices are referenced to the rising edge of the synchronous clock.
SRAM devices in general, have certain data access time speed advantages when compared to DRAM, with the latter requiring periodic refresh and bit line precharge operations. However, each SRAM memory cell requires four or six transistors per cell, and a DRAM memory cell can be constructed utilizing only a single transistor and associated capacitor (i.e. 1T/1C). Consequently, a typical SRAM device consumes on the order of four times more die area and two times the power of a corresponding DRAM. Ultimately, a SRAM of the same density of a DRAM will cost five to ten times more. Thus, there is a significant cost premium associated with the better SRAM performance.
SUMMARY OF THE INVENTION
The present invention advantageously provides an enhanced bus turnaround DRAM device which provides much of the same benefits of a conventional ZBT SRAM device with a similar pin-out, timing and function set while also providing improvements in device density, power consumption and cost. Through the provision of a “Wait” pin, the enhanced bus turnaround device of the present invention can signal the system memory controller when additional wait states must be added. Yet, it still provides virtually identical data access time performance to that of ZBT SRAM for all Read and Write operations with a burst length of four times or greater.


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EP 01300890.9 Communication dated Jul. 3, 2001, with Partial European Search Report.

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