Encoder/decoder with serial concatenated structure in...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction

Reexamination Certificate

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Details

C714S781000

Reexamination Certificate

active

06625775

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to an encode/decoder in a radio communication system, and in particular, to a device for encoding/decoding linear block codes through an analysis of serial concatenated codes.
2. Description of the Related Art
In the current state of the art, it is very difficult to perform complete soft decision on linear block codes. This technical field is related to soft decision of error correction codes and optimal performance of linear block codes, and in particular, to a decoding method for turbo codes. In addition, this field is extensively related to reliability improvement of digital communication systems, including not only existing digital communication systems but also future mobile communication systems using linear block codes.
Referring to
FIG. 1
, there is shown a block diagram illustrating a conventional device for encoding and decoding an (n,k) linear block. An encoder
111
and a decoder
112
perform the encoding and decoding of the signals.
Conventionally, erasure decoding and trellis decoding are used for soft decision of the linear block codes. However, such decoding methods are disadvantageous in that an increase in redundancy (n−k) of the linear block codes causes geometric progression of the complexity. Ideally, for a (n,k) linear block code, it is possible to perform soft decision by determining a trellis having 2
(n−k)
states and then performing maximum likelihood (ML) decoding on the trellis. However, since most linear block codes have a great number of redundancy bits, the actual complexity increases exponentially, which makes it difficult to implement the decoding method. In addition, since the existing ML (Maximum likelihood) decoding uses a method of determining an ML (maximum likelihood) codeword, it is not a preferable method for minimizing a post information bit error probability. Therefore, a decoding method for minimizing the post information bit error probability is required.
The above-stated conventional decoding method has the following disadvantages:
First, an increase in redundancy (n−k) of the linear block codes causes geometric progression of the complexity. In addition, since the linear block codes have a great number of redundancy bits, the actual complexity increases exponentially, thus making it difficult to implement the decoding method.
Second, the conventional method is not a preferable method for minimizing the post information bit error probability. Therefore, a method for minimizing the post information bit error probability is required.
Third, erasure decoding is not optimal decoding, but suboptimal decoding.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a device for encoding linear block codes based on serial concatenation in a communication system.
It is another object of the present invention to provide a device for decoding linear block codes based on serial concatenation in a communication system.
To achieve the above objects, a decoding device for decoding an input codeword bit stream using a generator polynomial represented by product of a plurality of sub-polynomials is provided. The decoding device comprises a plurality of serial concatenated decoders each having different generator polynomials, wherein a product of the different generator polynomials becomes said generator polynomial, the different generator polynomials are represented by the different sub-polynomials or by a product of the sub-polynomials, and a firststage decoder out of the serial concatenated decoders receives said codeword bit stream. The decoders each perform soft decision, and the codeword is a linear block code.
In addition, there is provided an encoding device for encoding input information bits using a generator polynomial represented by a product of a plurality of sub-polynomials. The encoding device comprises a plurality of serial concatenated encoders each having different respective generator polynomials, wherein said generator polynomial is a product of the respective generator polynomials and each respective generator polynomial is represented by one of the plurality of sub-polynomials or by a product of sub-polynomials, and a first-stage encoder out of the serial concatenated encoder receives said input information bits.


REFERENCES:
patent: 5721745 (1998-02-01), Hladik et al.
patent: 5983383 (1999-11-01), Wolf
patent: 5996104 (1999-11-01), Herzberg
patent: 6023783 (2000-02-01), Divsalar et al.
patent: 6192501 (2001-02-01), Hladik et al.
patent: 06-205054 (1994-07-01), None
patent: 07-022968 (1995-01-01), None
patent: 08-251144 (1996-09-01), None
patent: 10-154942 (1998-06-01), None
patent: WO 99/12265 (1999-03-01), None
patent: 11-215012 (1999-08-01), None
“Iterative MAP decoding for serial concatenated convolutional codes”, Ambroze, Wade, Tomlinson; IEEE Proceedings on Communications; vol. 145, No. 2, Apr. 1998, pp. 53-59.*
“Serial Concatenation of Interleaved Codes: Performance Analysis, Design, and Iterative Decoding”, Benedetto, Divsalar, Montorsi, Pollara; IEEE Transactions on Information Theory, vol. 44, No. 3, May 1998, pp. 909-926.*
“Serial Concatenation of Block and Convolutional Codes”, Benedetto, Montorsi; IEEE Electronic Letters, vol. 32, No. 10, May 9th, 1996, pp. 887-888.*
“A Soft-Input Soft-Output Maximum A Posteriori (MAP) Module to Decode Parallel and Serial Concatenated Codes”, Benedetto, Divsalar, Montorsi, Pollara; TDA Progress Report 42-127 for NASA and Cal Tech JPL, Nov. 15th, 1996, pp. 1-20.*
Japanese Office Action dated Sep. 17, 2002 issued in a counterpart application, namely, Appln. No. 2000-587451.
Japanese Office Action dated Mar. 25, 2003, issued in a counterpart application, namely, Appln. No. 2000-587451.

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