Encapsulated low resistance gate structure and method for formin

Details Encapsulated low resistance gate structure and method for formin Encapsulated low resistance gate structure and method for formin

2000-04-06

2000-12-12

Niebling, John F.

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

438595, H01L 213205, H01L 214763

Patent

active

061598356

ABSTRACT:
An encapsulated gate structure includes a polysilicon layer, a barrier layer overlying the polysilicon layer and having opposing sidewalls, a metal layer overlying the barrier layer and having opposing sidewalls, a top dielectric layer overlying the metal layer and having opposing sidewalls, and a vertically oriented dielectric layer extending over and covering each of the opposing sidewalls of the barrier layer and the metal layer to encapsulate the barrier layer and metal layer on the polysilicon layer. The encapsulated gate and barrier layer are thus unaffected by oxidation and other similar detrimental effects of subsequent processing steps.

REFERENCES:
patent: 5349228 (1994-09-01), Neudeck et al.
patent: 5382540 (1995-01-01), Sharma et al.
patent: 5397909 (1995-03-01), Moslehi
patent: 5925918 (1999-07-01), Wu et al.
patent: 5998290 (1999-12-01), Wu et al.
patent: 6075274 (2000-06-01), Wu et al.

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