Active solid-state devices (e.g. – transistors – solid-state diode – Encapsulated – With specified encapsulant
Reexamination Certificate
1998-09-16
2001-06-12
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Encapsulated
With specified encapsulant
C257S772000, C257S787000, C257S778000, C257S779000, C438S108000, C438S126000
Reexamination Certificate
active
06246124
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to semiconductor chip packages and, more particularly, to overmold or “glob-top” semiconductor chip carriers and to a related method of manufacturing such chip carriers.
BACKGROUND OF INVENTION
It is frequently desirable to encapsulate electronic devices, such as semiconductor dies, mounted on the surface of a substrate. Such semiconductor dies are electrically coupled to circuitry on the substrate, such as by wire bonding or by solder bumps. Encapsulation serves a variety of purposes.
One of the main purposes of encapsulation is to shield the encapsulated component from the environment and the contaminants of the environment. Encapsulation generally is accomplished by depositing a flowable dielectric material, such as an epoxy resin, on top of the electronic component and substrate to be encapsulated. One technique is to form an “overmold” by transfer molding. Transfer molding involves the use of dielectric material in the form of thermoset plastic which is injected at relatively high temperatures and under high pressures into a metal die cavity.
A related method, known as “flow forming” or “glob-top packaging,” also uses a thermoset plastic, dielectric, epoxy material. The process generally requires lower temperatures than transfer molding. Flow forming uses the lower viscosity of the flowable material and a dam around the periphery of the area to be encapsulated. The dam constrains the lateral flow of the dielectric material to the desired region to be encapsulated.
Unfortunately, certain semiconductor package configurations are prone to having the overlying glob-top or overmold encapsulant separate or “delaminate” from its position encapsulating the semiconductor die. Such separation or delamination exposes the semiconductor die to the environment and thus defeats one of the main purposes of encapsulation, that is, isolating the semiconductor die. This delamination problem is often aggravated when the underlying substrate carrying the encapsulant is non-rigid or flexible, because such flexibility often reduces the strength of adhesive bonding between the substrate and the encapsulant. The industry tendency towards miniaturization and ever larger semiconductor dies also tends to reduce the available surface area to which the encapsulant can bond, another factor which increases the likelihood of separation or delamination.
Attempts to counteract the delamination problem have had mixed results at best. For example, one approach, disclosed in U.S. Pat. No. 5,336,931 issued to Juskey, requires the additional processing step of drilling holes through the substrate at multiple, selected locations, and allowing the encapsulant material to flow into such holes. Among the drawbacks to this approach is the need to place such holes in “unused real estate” of the substrate and in a way that does not interfere with subsequent wire bonding steps. Furthermore, the addition of such holes may also tend to weaken the substrate and concentrate stresses, a drawback which becomes all the more significant when dealing with thinner or more structurally fragile substrates.
The unavailability of locations to drill such holes and the concern for the structural integrity of the substrate may also limit the size that such holes can attain, as well as the amount of dielectric material that the holes can receive. A limitation on the amount of dielectric material received in the holes limits, in turn, the additional adhesive strength imparted to the bond between the encapsulant and the substrate.
Another attempt to address the delamination tendency has been to add plasma treatment operations to the solder mask. Such operations “roughen” the surface of the solder mask against which the encapsulant adheres. The rougher surface makes it easier for the encapsulant to remain bonded. Even with this process improvement, however, an unacceptably high percentage of glob-top modules are rejected for delamination problems.
Therefore, a need remains to enhance the adhesion of overmold or glob-top encapsulant to its underlying substrate. There is a further need to enhance such adhesion without increasing the cost of manufacturing semiconductor chip carriers. A still further need, unmet in the prior art, is to enhance the adhesion of overmold or glob-top encapsulant to its underlying substrate without adding significant manufacturing steps.
SUMMARY OF THE INVENTION
To meet these and other needs, and in view of its purposes, the present invention, in one aspect, provides a semiconductor chip module. The chip module has an overmold or glob-top encapsulant adhered to one of its surfaces. The chip module includes a substrate which has a first, substantially planar surface. The planar surface of the substrate includes circuitized areas and bare areas without circuits on the bare areas. The semiconductor chip is positioned on the substrate and electrically coupled to the substrate.
A first dielectric layer is interposed between the first surface of the substrate and the chip. A second dielectric layer covers the chip to form the overmold or glob-top encapsulant. The semiconductor chip module is structured so that the encapsulating, second dielectric layer can be bonded integrally and directly to the first surface of the substrate. Such bonding enhances the adhesion of the second dielectric layer to the substrate.
In accordance with another aspect of the present invention, the semiconductor chip module has at least one anchor opening defined in portions of the first dielectric layer and located to expose a corresponding, substantially planar bare area of the substrate. The second dielectric layer is bonded to the substrate in part by having some of the dielectric material flowably received into the anchor opening, deposited on the corresponding bare area, and adhered to such area.
In accordance with another aspect of the present invention, the first dielectric layer is composed of a solder mask, and the second dielectric layer comprises a thermoset plastic material. The anchor openings in the solder mask are located at least about 0.010 to about 0.020 inches from the perimeter of the dielectric layer deposited on the substrate.
A method according to the present invention includes the steps of applying the first dielectric layer to preselected areas of the surface of a circuitized substrate but not to other areas of such surface. In this way, anchor openings are formed in the first dielectric layer and corresponding areas of the substrate are exposed by such anchor openings. The electronic component is positioned on the circuitized substrate and electrically coupled to the substrate. Thereafter, a second dielectric layer is applied to the electronic component, to the first dielectric layer, and to the exposed areas of the substrate which span the anchor openings of the first dielectric layer. The second dielectric layer flows into the anchor openings to form an integral chip cover which extends between the chip surface and the exposed areas of the circuitized substrate.
REFERENCES:
patent: 4625227 (1986-11-01), Hara et al.
patent: 5136366 (1992-08-01), Worp et al.
patent: 5229642 (1993-07-01), Hara et al.
patent: 5256903 (1993-10-01), Obata et al.
patent: 5336931 (1994-08-01), Juskey et al.
patent: 5440169 (1995-08-01), Tomita et al.
patent: 5535101 (1996-07-01), Miles et al.
patent: 5539257 (1996-07-01), Hara et al.
patent: 5552639 (1996-09-01), Hara et al.
patent: 5583381 (1996-12-01), Hara et al.
patent: 5763295 (1998-06-01), Tokuno et al.
patent: 5869886 (1999-02-01), Tokuno
patent: 5981314 (1999-11-01), Glenn et al.
patent: 62-92345 (1987-04-01), None
patent: 62-241358 (1987-10-01), None
patent: 1-152750 (1989-06-01), None
R. A. Christiansen and L. R. Steward, Semiconductor Die Encapsulant with Intrinsic Release Layer, IBM Technical Disclosure Bulletin, Vo. 34, No. 2, pp. 181-182 (Jul.-1991).
Jimarez Miguel A.
Perrino Marybeth
Tran Son K.
Wu Tien Y.
Chaudhuri Olik
International Business Machines - Corporation
Rao Shrinivas H.
Ratner & Prestia
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