Enabling memory redundancy during testing

Details Enabling memory redundancy during testing Enabling memory redundancy during testing

2007-12-04

2007-12-04

Nguyen, VanThu (Department: 2824)

Static information storage and retrieval

Read/write circuit

Testing

C365S200000

Reexamination Certificate

active

11160268

ABSTRACT:
Methods and apparatuses for enabling a redundant memory element (20) during testing of a memory array (14). The memory array (14) includes general memory elements (18) and redundant memory elements (20). The general memory elements (18) are tested and any defective general memory elements (18) are replaced with redundant memory elements (20). The redundant memory elements (20) are tested only when they are enabled.

REFERENCES:
patent: 4819205 (1989-04-01), McRoberts
patent: 5838623 (1998-11-01), Pascucci
patent: 5907514 (1999-05-01), Lee et al.
patent: 5936907 (1999-08-01), Pascucci
patent: 6367042 (2002-04-01), Phan et al.
patent: 6640321 (2003-10-01), Huang et al.
patent: 6691264 (2004-02-01), Huang

Affiliated with

Also associated with

Rating

Enabling memory redundancy during testing does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Enabling memory redundancy during testing, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Enabling memory redundancy during testing will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3879903