Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses – Using delay
Reexamination Certificate
2000-05-11
2004-02-24
Butler, Dennis M. (Department: 2185)
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
Using delay
C713S001000, C713S503000
Reexamination Certificate
active
06697957
ABSTRACT:
FIELD OF THE INVENTION
The field of the invention relates generally to an integrated circuit chip for an emulation system; and, more particularly to an improved logic element for an emulation system with a hold time algorithm that eliminates race time problems.
BACKGROUND OF THE INVENTION
General purpose programmable logic chips that are available as off-the-shelf components (i.e., are commercially available) are generally not custom designed for special applications such as logic emulation, prototyping and computing. Examples of general purpose programmable logic chips are field programmable gate arrays (“FPGAs”), programmable logic arrays (“PLAs”) and programmable array logic (“PALs”). General-purpose programmable logic chips have served adequately in the initial development of applications such as hardware logic emulation, prototyping and computing. However, in these applications, general-purpose logic chips have some drawbacks. Many general-purpose logic chips emphasize speed and density (i.e., how many logic gates can be implemented in a single chip) above other goals. To be cost effective for most applications, a general-purpose programmable logic architecture should provide routing resources sufficient to give a good chance of fitting a design therein and allowing the use of most of the available logic gates in the integrated circuit. However, with a general-purpose programmable logic architecture, there is always a possibility that a given design or partition may not be implementable, even though the gate count (i.e., the number of gates that the manufacturer of the programmable logic chip claims the chip can implement) is within the rated capacity of the chip. Also, the speed of the compile process is of lesser importance in the general purpose logic chip.
In contrast, in a logic emulation, prototyping or computing application, the priorities are different. The logic chip is normally part of a larger, multi-chip system, often with tens or hundreds of logic chips. Large input design netlists must be automatically compiled into all these logic chips with a very high degree of success and a minimum of user intervention. A netlist is a description of a logic design that specifies the components of the design (e.g., the logic gates) and how the components are interconnected. Each “net” of a netlist defines a circuit path between pins on a component or an input/output pad. It is essential that the logic chip used in these applications provide routing resources which are flexible and capable enough to nearly always succeed in allowing most of the logic resources to be used by a fully automatic compile process. This compile process should execute rapidly. Fast compile times minimize the time required to get from the time the user's design is presented to the emulator system to the time all the logic chips are programmed and ready to run the user's design (i.e., emulate the user's design).
The differences between the goals of the general purpose logic chip and the goals of a logic chip used in emulation, prototyping and computing applications present a situation where there is a need for a logic chip which is specialized for logic emulation, prototyping and computing applications.
Moreover, the design and interconnect flexibility of integrated circuits used for emulation should reduce the probability of routing failure as much as possible, result in high predictability of the capacity of gates which can be emulated, and resolve certain timing problems. A common problem with partitioning very large designs into a large number of programmable logic chips is that the timing of the original netlist is not preserved. The natural partitions of the original design probably reflect the timing in the final single chip implementation. However, the software which decomposes and re-partitions the netlist onto a programmable logic target must impose a different partitioning for that target. Signal path delays are expanded, and not uniformly. These differential expansions of delays may introduce timing problems (i.e., skews, setup and hold violations) which are not inherent in the design netlist. Occasionally, timing problems which are present in the design netlist will be hidden by the mapping onto the programmable logic system. Both of these timing problems may be unsatisfactory to a user or emulator. An emulation architecture must detect introduced timing problems and have the hardware for removing these timing problems.
Emulation integrated circuits are traditionally structured in a multi-level hierarchy, with simple logic blocks capable of performing the desired logic functions combined together to form more complex blocks, which are then combined to form a complete chip. Typically, the amount of interconnect is greatest at the lowest level of the hierarchy and decreases at the upper levels. Consequently, the design of the lowest level interconnect has a large effect on overall chip size and cost.
Interconnect at the lowest level of the hierarchy has traditionally been achieved through either (1) a partially populated multiplexer structure which interconnects rows and columns of logic elements (employed, for example, in the Xilinx 4000 series FPGAs), or (2) a full crossbar which interconnects a small group of logic elements (employed, for example, in the Altera Flex 8000 family of FPGAs). However, the partially populated multiplexer structure suffers from limited routing flexibility. Circuit designs which require many local connections from one logic element to another may not be routable at all in a given chip, or alternately, may require very complex software and long computation times in order to complete routing between logic elements.
A full crossbar interconnect at the lowest level of the hierarchy avoids the problems of a partially populated multiplexer interconnect by guaranteeing complete interconnectivity between a small group of logic elements. The drawback to a full crossbar interconnect scheme, however, is the amount of silicon required to implement a full crossbar. Required silicon area is proportional to the square of the number of logic elements being interconnected. Thus, only a small number of logic elements can be interconnected via full crossbar before the cost becomes prohibitive. By way of example, the lowest level block in the Altera Flex 8000 chip has eight logic elements. It is difficult to construct large integrated circuits using such small low-level blocks, because excessive numbers of blocks and interconnect signals are needed at higher levels in the chip.
Because the logic element is the fundamental building block of a logic block which in turn is used to build an integrated circuit chip for an emulation system, improvements in the logic element are needed in order to achieve greater accuracy and efficiency in emulation. Race time problems and other performance related issues create a need to improve present day logic elements. There is also a need to provide testing and probing functions.
Further limitations and disadvantages of conventional systems and circuits will become apparent to one of skill in the art after reviewing the remainder of the present application with reference to the figures.
SUMMARY OF THE INVENTION
Various separate aspects of the invention can be found in an improved circuit for an emulation system. The improved circuit has a logic element having a RAM, lookup table, optional delay element and flip flop/latch. The flip/flop latch may behave as a flip flop or as a latch and has separate set and reset signals. The delay element inserts a selectable amount of delay into the data path of the logic element in order to reduce race time problems. The logic elements may be combined to share input signals so as to increase the size of the RAM. The improved circuit also has a shadow memory used to store sampled data from a logic element and to playback emulation data for debugging purposes. Multiple read ports permit a user to read out data from the improved circuit during emulation in a time multiplexed manner. The input/outpu
Carrell William C.
Shei Swey-Yan
Wang Ming Yang
Butler Dennis M.
Orrick Herrington & Sutcliffe LLP
Quickturn Design Systems Inc.
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