Electrical computers and digital processing systems: processing – Processing control – Specialized instruction processing in support of testing,...
Reexamination Certificate
1999-10-01
2002-09-10
Treat, William M. (Department: 2783)
Electrical computers and digital processing systems: processing
Processing control
Specialized instruction processing in support of testing,...
C712S043000, C712S209000, C712S226000, C712S229000, C712S233000, C712S234000, C703S026000
Reexamination Certificate
active
06449712
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates generally to microprocessor/microcontroller architecture, and particularly to an architecture structured to execute a first fixed-length instruction set with backward compatibility to a second, smaller fixed instruction.
Recent advances in the field of miniaturization and packaging in the electronics industry has provided the opportunity for the design of a variety of “embedded” products. Embedded products are typically small and hand-held, and are constructed to include micro-controllers or microprocessors for control functions. Examples of embedded products include such handheld business, consumer, and industrial devices as cell phones, pagers and personal digital assistants (PDAs).
A successful embedded design or architecture must take into consideration certain requirements such as the size and power consumption of the part to be embedded. For this reason, some micro-controllers and microprocessors for embedded products are designed to incorporate Reduced Instruction Set Computing (RISC) architecture which focuses on rapid and efficient processing of a relatively small set of instructions. Earlier RISC designs, however, used 32-bit, fixed-length instruction sets. To further minimize the processing element, designs using small fixed size, such as 16-bit were developed, enabling use of compact code to reduce the size of the instruction memory. RISC architecture coupled with small, compact code permits the design of embedded products to be simpler, smaller, and power conscious. An example of such a 16-bit architecture is disclosed in U.S. Pat. No. 5,682,545.
However, the need for more computing capability and flexibility than can be provided by a 16-bit instruction set exists, and grows, particularly when the capability for graphics is desired. To meet this need, 32-bit instruction set architectures are being made available. With such 32-bit instruction set architectures, however, larger memory size for storing the larger 32-bit instructions is required. Larger memory size, in turn, brings with it the need for higher power consumption and more space, requirements that run counter to the design of successful embedded products.
Also, present 32-bit instruction set architectures provide little, if any, backward compatibility to earlier-developed, 16-bit code. As a result, substantial software investments are lost. Thus, applications using the prior, smaller, code must be either discarded or recompiled to the 32-bit instruction.
Thus, it can be seen that there is a need to provide a 32-bit instruction architecture that imposes a negligible impact on size and power consumption restraints, as well as providing a backward compatibility to earlier instruction set architectures.
SUMMARY OF THE INVENTION
Broadly, the present invention is directed to a processor element, such as a microprocessor or a micro-controller, structured to execute either a larger fixed-length instruction set architecture or an earlier-designed, smaller fixed-length instruction set architecture, thereby providing backward compatibility to the smaller instruction set. Execution of the smaller instruction set is accomplished, in major part, by emulating each smaller instruction with a sequence of one or more of the larger instructions. In addition, resources (e.g., registers, status bits, and other state) of the smaller instruction set architecture are mapped to the resources of the larger instruction set environment.
In an embodiment of the invention, the larger instruction set architecture uses 32-bit fixed-length instructions, and the smaller instruction set uses 16-bit fixed length instructions. However, as those skilled in this art will see, the two different instruction sets may be of any length. A first group of the 16-bit instructions will each be emulated by a single 32-bit instruction sequence. A second group of the 16-bit instructions are each emulated by sequences of two or more of the 32-bit instructions. Switching between the modes of execution is accomplished by branch instructions using target addresses having a bit position (in the preferred embodiment the least significant bit (LSB)) set to a predetermined state to identify that the target of the branch is a member of one instruction set (e.g., 16-bit), or to the opposite state to identify the target as being a member of the other instruction set (32-bit).
The particular 16-bit instruction set architecture includes what is called a “delay slot” for branch instructions. A delay slot is the instruction immediately following a branch instruction, and is executed (if the branch instruction so indicates) while certain aspects of the branch instruction are set up, and before the branch is taken. In this manner, the penalty for the branch is diminished. Emulating a 16-bit branch instruction that is accompanied by a delay slot instruction is accomplished by using a prepare to branch (PT) instruction in advance of the branch instruction that loads a target register. The branch instruction then uses the content of the target register for the branch. However, when emulating a 16-bit branch instruction with a delay slot requirement, the branch is executed, but the target instruction (if the branch is taken) is held in abeyance until emulation and execution of the 16-bit delay slot instruction completes.
The 32-bit PT instruction forms a part of a control flow mechanism that operates to provide low-penalty branching in the 32-bit instruction set environment by separating notification of the processor element of the branch target from the branch instruction. This allows the processor hardware to be made aware of the branch many cycles in advance, allowing a smooth transition from the current instruction sequence to the target sequence. In addition, it obviates the need for the delay slot technique use in the 16-bit instruction set architecture for minimizing branch penalties.
A feature of the invention provides a number of general purpose registers, each 64-bits in length, for use by either the 16-bit instructions or the 32-bit instructions. However, when a general purpose register is written or loaded by a 16-bit instruction, only the low order 32-bits are used. In addition, an automatic extension of the sign bit is performed when most 16-bit instructions load a general purpose register; that is, the most significant bit of the 32-bit quantity placed in the low-order bit positions of a 64-bit general purpose register are copied to all 32 of the high-order bits of the register. The 32-bit instruction set architecture includes instructions structured to use this protocol, providing compatibility between the 16-bit and 32-bit environments.
Also, a 64-bit status register is provided for both the 16-bit instruction set and the 32-bit instruction set. Predetermined bit positions of the status register are reserved for state that is mapped from the 16-bit instruction set. Other of the 16-bit state is mapped to predetermined bit positions of certain of the general purpose registers. This mapping of the 16-bit instruction set state allows separate environments (16-bit, 32-bit) to save all necessary context on task switching, and facilitates emulation of the 16-bit instructions with 32-bit instructions.
A number of advantages are achieved by the present invention. The ability to execute both 16-bit code and 32-bit code allows a processor to use the compact, 16-bit code for the mundane tasks. This, in turn, allows a saving of both memory space and the other advantages attendant with that saving (e.g., smaller memory, reduced power consumption, and the like). The 32-bit code can be used when more involved tasks are needed.
Further, the ability to execute an earlier-designed 16-bit instruction set architecture provides a compatibility that permits retention of the investment made in that earlier design.
The PT instruction, by providing advance notice of a branch, allows for more flexibility in the performance of branch instructions.
These and other advantages and features of the present invention will become apparent to t
Freeman Jackie A.
Irie Naohiko
Krishnan Sivaram
Peng Chih-Jui
Werner Tony Lee
Hitachi , Ltd.
Townsend & Townsend and Crew LLP
Treat William M.
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