Electronic digital logic circuitry – Multifunctional or programmable – Array
Reexamination Certificate
2007-07-10
2007-07-10
Tran, Anh Q. (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Array
C326S041000, C326S047000, C326S040000
Reexamination Certificate
active
11081809
ABSTRACT:
Some embodiments of the invention provide a configurable IC that includes several configurable computational tiles and several memory tiles. These tiles are arranged in a particular tile arrangement. Each computational tile has a set of configurable logic circuits for configurably performing a plurality of computations and a set of configurable routing circuits. The routing circuits of the tiles configurably route signals between configurable logic circuits. The configurable IC also has several memory arrays for storing data on which the logic circuit perform computation. The memory arrays are embedded in the tile arrangement between two sets of memory tiles, where each set of memory tiles includes a set of routing circuits. In this IC, at least a first memory tile has the same set of configurable routing circuits as at least a second computational tile.
REFERENCES:
patent: 4873459 (1989-10-01), El Gamal et al.
patent: 5245575 (1993-09-01), Sasaki et al.
patent: 5349250 (1994-09-01), New
patent: 5357153 (1994-10-01), Chiang et al.
patent: 5365125 (1994-11-01), Goetting et al.
patent: 5369622 (1994-11-01), McLaury
patent: 5426378 (1995-06-01), Ong
patent: 5521835 (1996-05-01), Trimberger
patent: 5532958 (1996-07-01), Jiang et al.
patent: 5552721 (1996-09-01), Gould
patent: 5610829 (1997-03-01), Trimberger
patent: 5631578 (1997-05-01), Clinton et al.
patent: 5646544 (1997-07-01), Iadanza
patent: 5659484 (1997-08-01), Bennett et al.
patent: 5682107 (1997-10-01), Tavana et al.
patent: 5692147 (1997-11-01), Larsen et al.
patent: 5694057 (1997-12-01), Gould
patent: 5719889 (1998-02-01), Iadanza
patent: 5732246 (1998-03-01), Gould et al.
patent: 5737235 (1998-04-01), Kean et al.
patent: 5745422 (1998-04-01), Iadanza
patent: 5745734 (1998-04-01), Craft et al.
patent: 5764954 (1998-06-01), Fuller et al.
patent: 5768178 (1998-06-01), McLaury
patent: 5777360 (1998-07-01), Rostoker et al.
patent: 5802003 (1998-09-01), Iadanza et al.
patent: 5815726 (1998-09-01), Cliff
patent: 5889411 (1999-03-01), Chaudhary
patent: 5914616 (1999-06-01), Young et al.
patent: 5914906 (1999-06-01), Iadanza et al.
patent: 5982655 (1999-11-01), Doyle
patent: 6002991 (1999-12-01), Conn, Jr.
patent: 6023421 (2000-02-01), Clinton et al.
patent: 6038192 (2000-03-01), Clinton et al.
patent: 6044031 (2000-03-01), Iadanza et al.
patent: 6054873 (2000-04-01), Laramie
patent: 6069490 (2000-05-01), Ochotta et al.
patent: 6075745 (2000-06-01), Gould et al.
patent: 6086631 (2000-07-01), Chaudhary et al.
patent: 6091263 (2000-07-01), New et al.
patent: 6091645 (2000-07-01), Iadanza
patent: 6107821 (2000-08-01), Kelem et al.
patent: 6110223 (2000-08-01), Southgate et al.
patent: 6118707 (2000-09-01), Gould et al.
patent: 6130854 (2000-10-01), Gould et al.
patent: 6134154 (2000-10-01), Iwaki et al.
patent: 6140839 (2000-10-01), Kaviani et al.
patent: 6150838 (2000-11-01), Wittig et al.
patent: 6163168 (2000-12-01), Nguyen et al.
patent: 6172521 (2001-01-01), Motomura
patent: 6173379 (2001-01-01), Poplingher et al.
patent: 6175247 (2001-01-01), Scalera et al.
patent: 6184707 (2001-02-01), Norman et al.
patent: 6184709 (2001-02-01), New
patent: 6205076 (2001-03-01), Wakayama et al.
patent: 6233191 (2001-05-01), Gould et al.
patent: 6275064 (2001-08-01), Agrawal et al.
patent: 6292019 (2001-09-01), New et al.
patent: 6326807 (2001-12-01), Veenstra et al.
patent: 6346824 (2002-02-01), New
patent: 6348813 (2002-02-01), Agrawal et al.
patent: 6381732 (2002-04-01), Burnham et al.
patent: 6469540 (2002-10-01), Nakaya
patent: 6487709 (2002-11-01), Keller et al.
patent: 6490707 (2002-12-01), Baxter
patent: 6496918 (2002-12-01), DeHon et al.
patent: 6515509 (2003-02-01), Baxter
patent: 6526559 (2003-02-01), Schiefele et al.
patent: 6529040 (2003-03-01), Carberry et al.
patent: 6545501 (2003-04-01), Bailis et al.
patent: 6593771 (2003-07-01), Bailis et al.
patent: 6601227 (2003-07-01), Trimberger
patent: 6603330 (2003-08-01), Snyder
patent: 6629308 (2003-09-01), Baxter
patent: 6636070 (2003-10-01), Altaf
patent: 6642744 (2003-11-01), Or-Bach et al.
patent: 6650142 (2003-11-01), Agrawal et al.
patent: 6667635 (2003-12-01), Pi et al.
patent: 6668361 (2003-12-01), Bailis et al.
patent: 6675309 (2004-01-01), Baxter
patent: 6714041 (2004-03-01), Darling et al.
patent: 6732068 (2004-05-01), Sample et al.
patent: 6806730 (2004-10-01), Bailis et al.
patent: 6809979 (2004-10-01), Tang
patent: 6831479 (2004-12-01), Lo
patent: 6838902 (2005-01-01), Elftmann et al.
patent: 6920627 (2005-07-01), Blodget et al.
patent: 6924663 (2005-08-01), Masui et al.
patent: 6937535 (2005-08-01), Ahn et al.
patent: 6956399 (2005-10-01), Bauer
patent: 6992505 (2006-01-01), Zhou
patent: 6998872 (2006-02-01), Chirania et al.
patent: 7010667 (2006-03-01), Vorbach et al.
patent: 7028281 (2006-04-01), Agrawal et al.
patent: 7075333 (2006-07-01), Chaudhary et al.
patent: 7126372 (2006-10-01), Vadi et al.
patent: 7126856 (2006-10-01), Sun et al.
patent: 7129746 (2006-10-01), Balasubramanian et al.
patent: 2001/0007428 (2001-07-01), Young et al.
patent: 2002/0008541 (2002-01-01), Young et al.
patent: 2002/0113619 (2002-08-01), Wong
patent: 2002/0125914 (2002-09-01), Kim
patent: 2002/0161568 (2002-10-01), Sample et al.
patent: 2002/0163357 (2002-11-01), Ting
patent: 2003/0042931 (2003-03-01), Ting
patent: 2003/0080777 (2003-05-01), Baxter
patent: 2003/0110430 (2003-06-01), Bailis et al.
patent: 2004/0010767 (2004-01-01), Agrawal et al.
patent: 2004/0103265 (2004-05-01), Smith
patent: 2004/0196066 (2004-10-01), Ting
patent: 2004/0233758 (2004-11-01), Kim et al.
patent: 2005/0007155 (2005-01-01), Young
patent: 2005/0134308 (2005-06-01), Okada et al.
“Design for Low Power in Actel Antifuse FPGAs”, Actel Application Note, 2000 Actel Corporation Sep. 2000, pp. 1-8.
Quicklogic Corp., “Ultra-Low Power FPGA Combining Performance, Density, and Embedded RAM,”Eclipse II Family Data Sheet, 2005, pp. 1-92, QuickLogic Corporation, US??, no month.
Cong, J., et al., “Combinational Logic Synthesis for LUT Based Field Programmable Gate Arrays,”ACM Transactions on Design Automation of Electronic Systems, Apr. 1996, pp. 145-204, vol. 1, No. 2, ACM, Inc.
Snider, G., “Performance-Constrained Pipelining of Software Loops onto Reconfigurable Hardware,”FPGA '02, Feb. 24-26, 2002, pp. 177-186, ACM, Monterey, California, USA.
Singh, A., et al., “PITIA: An FPGA for Throughput-Intensive Applications,”IEEE Transactions on Very Large Scale Integration(VLSI)Systems, Jun. 2003, pp. 354-363, vol. 11, No. 3, IEEE.
Singh, A., et al., “Interconnect Pipelining in a Throughput-Intensive FPGA Architecture,”FPGA 2001, Feb. 11-13, 2001, pp. 153-160, ACM, Monterey, CA, USA.
Markovskiy, Y., et al., “Analysis of Quasi-Static Scheduling Techniques in a Virtualized Reconfigurable Machine,”FPGA '02, Feb. 24-26, 2002, ACM, Monterey, California, USA.
Caspi, E., et al., “Stream Computations Organized for Reconfigurable Execution (SCORE): Introduction and Tutorial,” Aug. 25, 2000, pp. 1-31, Version 1.0.
Camposano, R., “The Growing Semiconductor Zoo: ASICs, CSSP, ASSP, ASIP, Structured Arrays, FPGAs, Processor Arrays, Platforms . . . and Other Animalia,” 2003, pp. 1-74, Synopsys, Inc., no month.
Ohkura, J., et al., “Dataflow in the Adaptive Computing Machine (ACM),”A Technology Application Whitepaper, Apr. 28, 2004 but © 2003, pp. 1-9, QuickSilver Technology, Inc., San Jose, California.
Heidari, G., et al., “Introducing a Paradigm Shift in the Design and Implementation of Wireless Devices,”A Wireless Devices Whitepaper, Apr. 28, 2004 but © 2003, pp. 1-10, QuickSilver Technology, Inc., San Jose, California.
Plunkett, B., “In Search of the SDR Holy Grail, ”A Technology Application Whitepaper, Apr. 28, 2004 but © 2003, pp. 1-7, QuickSilver Technology, Inc., San Jose, California.
Sambhwani, S., et al., “Implementing W-CDMA Transciever Structure on an Adaptive Computing Platform,”A Technology Application Whitepaper, Apr. 28, 2004 but &#
Redgrave Jason
Schmit Herman
Adeli Law Group
Tran Anh Q.
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