Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-05-16
2004-04-27
Nhu, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S288000
Reexamination Certificate
active
06727539
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method for fabricating semiconductor circuits containing both DRAM and logic cells. In particular, the invention relates to fabricating semiconductor circuits containing vertical pass gate embedded DRAM (EDRAM) arrays and dual workfunction logic gates.
BACKGROUND OF THE INVENTION
With the advent of Large Scale Integration (LSI), many integrated circuit designs include several circuit functions on a single semiconductor substrate, such as memory storage and logic functions for addressing and accessing the memory. In the case where a logic region and a DRAM cell (memory) region are formed on the same substrate, the circuitry is commonly referred to as an embedded DRAM. The integration of logic and memory regions improves overall device performance by decreasing communication delays between memory devices on one chip and logic devices located on a second chip. In addition to the improvements in device performance, processing costs for integrating memory and logic circuit functions on the same semiconductor substrate potentially could be reduced due to the sharing of specific processing steps used to fabricate both types of devices. Present trends in DRAM technology are driving towards continued scaling of minimum feature size (F) in the DRAM array, and more compact cell layouts (e.g., 7F
2
, 6F
2
, etc.). As a result, the above noted problems in the prior art become even more problematic, especially for devices where F=100 nm and smaller.
DRAM circuits will usually include an array of memory cells interconnected by rows and columns, which are known as wordlines and bitlines, respectively. Reading data from, or writing data to the memory cells is achieved by activating selected wordlines and bitlines. Typically, the DRAM memory cell comprises a MOSFET (metal oxide semiconductor field effect transistor) connected to a capacitor. The MOSFET generally includes a gate region and diffusion regions. The diffusion regions, depending on the operation of the transistor, are often referred to as either drain or source regions.
There are different types of MOSFETs. Trench-gated MOSFETs are a class of MOSFETs in which the gate is positioned in a trench that is formed at the surface and extends into the silicon. The gate is formed in a lattice-like geometric pattern which defines individual cells of the DRAM; the pattern normally taking the form of closed polygons (squares, hexagons, etc.) or a series of interdigitated stripes or rectangles. The current flows in vertical channels which are formed adjacent to the sides of the trenches. The trenches are filled with a conductive gate material, typically doped polysilicon, which is insulated from the silicon by a dielectric layer normally consisting of silicon dioxide.
The trench-gated MOSFETs are normally formed by etching trenches of various dimensions into a silicon substrate. The gate trenches normally extend into the substrate and are frequently rectangular, with flat bottoms bounded by corners. Trenches commonly contain storage capacitors below the MOSFETs and have N+ doped polysilicon as one plate of the capacitor (a storage node). The other plate of the capacitor is formed usually by diffusing N+ dopants out from a dopant source into a portion of the substrate surrounding the lower part of the trench. Between these two plates a dielectric layer is placed which thereby forms the capacitor.
Typically, isolation regions are formed in the substrate to prevent carriers from traveling through the substrate between adjacent devices. The isolation regions are generally thick field oxide regions extending below the surface of the semiconductor substrate. One such technique for forming the isolation region is the local oxidation of silicon, i.e., LOCOS regions. LOCOS field oxidation regions are formed by first depositing a layer of silicon nitride on the substrate surface and then selectively etching a portion of the silicon nitride layer to form a mask exposing the substrate where the field oxidation will be formed. The masked substrate is then placed in an oxidation environment and a thick layer of oxide is selectively grown in the exposed mask regions forming an oxide layer extending above and below the substrate surface. An preferred alternative to LOCOS field oxidation is the formation of shallow trench isolation regions in contemporary CMOS technology, commonly referred to by those in the art as an STI region. In the process of forming the STI regions, a deep trench is formed in the semiconductor substrate by, for example, anisotropic etching. The trench is then filled with oxide back to the surface of the substrate to provide an isolation region between adjacent devices.
In a typical DRAM array, the wordlines need to be capped with an insulator to allow formation of borderless diffusion contacts, whereas in the logic supports the gate conductors must be exposed to allow the introduction of dual workfunction doping and silicidation. Silicided gates and source/drain regions greatly complicate the processes for forming array MOSFETs since the array MOSFETs need bitline contacts which are borderless to adjacent wordline conductors. In addition, it has been found that silicide junctions in the array frequently result in increased current leakage of the memory device. Conventional solutions to these integration problems require additional masking steps to remove the insulating gate cap from the support MOSFETs prior to the silicidation process.
Problems encountered in the formation of vertical pass gate embedded DRAM (EDRAM) arrays and dual workfunction logic gates include the lithography steps used to simultaneously form the support gates and wordlines. The wordlines used in the array have tight pitch requirements whereas the support regions have relatively relaxed pitch features. Lithographic patterning these different pitches typically requires complex solutions, such as alternating phase shift masking techniques and the like, to overcome these difficulties. It is desirable to have the pitch requirements for the array and supports be similar or more relaxed to overcome these well known lithographic problems. However, this is not currently feasible as circuitry density increases and as such, common practice is to separately pattern the array and supports.
Another problem with prior art processes is in the formation of the local interconnects. Conventionally, one of the metallization layers is used for forming both the bitline and the local interconnects. It is preferred to have a simpler process that eliminates the metallization layer and its attendant processing to form the local interconnect and metal layer. U.S. patent application Ser. No. 09/725,412 to Mandelman et al. filed on Nov. 29, 2000 shows how to form dual work function logic gates with vertical DRAM cells using a raised shallow trench isolation (RSTI) process. This process has the disadvantage that the support logic devices are subject to the thermal processes of the shallow trench isolation which can degrade the well profile.
U.S. patent application Ser. No. 09/706,492 to Mandelman et al. filed on Nov. 3, 2000 overcomes many of the above noted thermal problems. The process disclosed therein generally includes a) patterning only the array gate wiring for the vertical transistors; b) forming silicided bitlines and peripheral transistors concurrently and c) showing a metal to form local interconnects. However, this methodology becomes difficult to implement for tight array pitches patterned with 193 nm lithography.
Accordingly, there is a need for improved processes that address these concerns and provide a process that can be used for the more compact cell layouts.
BRIEF SUMMARY OF THE INVENTION
A process and structure for producing high density embedded DRAM and logic structures is described. The process includes fabricating embedded vertical DRAM arrays with a silicided bitline and a polysilicon interconnect. In one embodiment, the method of forming a memory array and support transistors on a semiconductor s
Divakaruni Ramachandra
Gruening Ulrike
Mandelman Jack A.
Nesbit Larry
Radens Carl
Blecker Ira D.
Cantor & Colburn LLP
Nhu David
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