Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device – With lattice constant mismatch
Reexamination Certificate
2005-05-10
2008-11-04
Fourson, George (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Heterojunction device
With lattice constant mismatch
C257S192000, C257S347000, C257SE29297, C257SE29299, C257SE21619, C438S151000, C438S285000
Reexamination Certificate
active
07446350
ABSTRACT:
Disclosed is a p-type field effect transistor (pFET) structure and method of forming the pFET. The pFET comprises embedded silicon germanium in the source/drain regions to increase longitudinal stress on the p-channel and, thereby, enhance transistor performance. Increased stress is achieved by increasing the depth of the source/drain regions and, thereby, the volume of the embedded silicon germanium. The greater depth (e.g., up to 100 nm) of the stressed silicon germanium source/drain regions is achieved by using a double BOX SOI wafer. Trenches are etched through a first silicon layer and first buried oxide layer and then the stressed silicon germanium is epitaxially grown from a second silicon layer. A second buried oxide layer isolates the pFET.
REFERENCES:
patent: 5268324 (1993-12-01), Aitken et al.
patent: 5583059 (1996-12-01), Burghartz
patent: 5882987 (1999-03-01), Srikrishnan
patent: 6121100 (2000-09-01), Andideh et al.
patent: 6365488 (2002-04-01), Liao
patent: 6432754 (2002-08-01), Assaderaghi et al.
patent: 6621131 (2003-09-01), Murthy et al.
patent: 6855982 (2005-02-01), Xiang et al.
patent: 6891192 (2005-05-01), Chen et al.
patent: 7102201 (2006-09-01), Furukawa et al.
patent: 7176522 (2007-02-01), Cheng et al.
patent: 7221006 (2007-05-01), Orlowski et al.
patent: 7288448 (2007-10-01), Orlowski et al.
patent: 7306997 (2007-12-01), Xiang et al.
patent: 2003/0057439 (2003-03-01), Fitzgerald
patent: 2005/0029601 (2005-02-01), Chen et al.
patent: 2005/0082531 (2005-04-01), Rim
patent: 2005/0093084 (2005-05-01), Wang et al.
patent: 2005/0130454 (2005-06-01), Murthy et al.
patent: 2005/0285192 (2005-12-01), Zhu
patent: 2006/0054968 (2006-03-01), Lee
patent: 2006/0065914 (2006-03-01), Chen et al.
patent: 2006/0166492 (2006-07-01), Orlowski et al.
patent: 2006/0231892 (2006-10-01), Furukawa et al.
U.S. Appl. No. 10/711,637 Title: “Structure And Method For Making Strained Channel Field Effect Transistor Using Sacrificial Spacer” Applicant: Chen, et al. Date filed: Sep. 29, 2004.
U.S. Appl. No. 10/453,080 Title: Method Of Forming Precision Recessed Gate Structure Applicant: Rausch, et al Date Filed: Jun. 3, 2003.
U.S. Appl. No. 10/605,134 Title: “Structure And Method Of Making Strained Channel CMOS Transistors Having Lattice-Mismatched Epitaxial Extension And Source And Drain Regions” Applicant: Chen, et al. Date Filed: Sep. 10, 2003.
U.S. Appl. No. 10/905,598 Title: “In Situ Doped Enbedded SiGe Extension And Source/Drain For Enhanced PFET Performance” Applicant: Chen, et al. Date Filed: Jan. 12, 2005.
Chen Huajie
Chidambarrao Dureseti
Schepis Dominic J.
Utomo Henry K.
Fourson George
Gibb & Rahman, LLC
International Business Machine Corporation
Li, Esq. Todd M.C.
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