Embedded silicon germanium using a double buried oxide...

Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device – With lattice constant mismatch

Reexamination Certificate

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Details

C257S192000, C257S347000, C257SE29297, C257SE29299, C257SE21619, C438S151000, C438S285000

Reexamination Certificate

active

07446350

ABSTRACT:
Disclosed is a p-type field effect transistor (pFET) structure and method of forming the pFET. The pFET comprises embedded silicon germanium in the source/drain regions to increase longitudinal stress on the p-channel and, thereby, enhance transistor performance. Increased stress is achieved by increasing the depth of the source/drain regions and, thereby, the volume of the embedded silicon germanium. The greater depth (e.g., up to 100 nm) of the stressed silicon germanium source/drain regions is achieved by using a double BOX SOI wafer. Trenches are etched through a first silicon layer and first buried oxide layer and then the stressed silicon germanium is epitaxially grown from a second silicon layer. A second buried oxide layer isolates the pFET.

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