Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device – With lattice constant mismatch
Reexamination Certificate
2005-09-15
2009-11-03
Wilson, Allan R. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Heterojunction device
With lattice constant mismatch
C257SE29277
Reexamination Certificate
active
07612389
ABSTRACT:
MOS devices having localized stressors are provided. Embodiments of the invention comprise a gate electrode formed over a substrate and source/drain regions formed on either side of the gate electrode. The source/drain regions include an embedded stressor and a capping layer on the embedded stressor. Preferably, the embedded stressor has a lattice spacing greater than the substrate lattice spacing. In a preferred embodiment, the substrate is silicon and the embedded stressor is silicon germanium. A method of manufacturing is also provided, wherein strained PMOS and NMOS transistors may be formed simultaneously.
REFERENCES:
patent: 4728619 (1988-03-01), Pfiester et al.
patent: 6051458 (2000-04-01), Liang et al.
patent: 6649538 (2003-11-01), Cheng et al.
patent: 6703271 (2004-03-01), Yeo et al.
patent: 6806151 (2004-10-01), Wasshuber et al.
patent: 6921913 (2005-07-01), Yeo et al.
patent: 7118952 (2006-10-01), Chen et al.
patent: 7166528 (2007-01-01), Kim et al.
patent: 2004/0087075 (2004-05-01), Wang et al.
patent: 2004/0115878 (2004-06-01), Lee et al.
patent: 2004/0157399 (2004-08-01), Lee et al.
patent: 2005/0035409 (2005-02-01), Ko et al.
patent: 2005/0093021 (2005-05-01), Ouyang et al.
patent: 2006/0189053 (2006-08-01), Wang et al.
patent: 2006/0267106 (2006-11-01), Chao et al.
Bedell, S.W., et al., “300 mm SGOI/Strained-Si for High-Performance CMOS,” 2004 Semiconductor Equipment and Materials International, Semicon West, (2004) 6 pages.
Chidambaram, P.R., et al., “35% Drive Current Improvement from Recessed-SiGe Drain Extensions on 37 nm Gate Length PMOS,” 2004 Symposium on VLSI Technology Digest of Technical Papers (2004) pp. 48-49.
Ghani, T., et al., “A 90nm High Volume Manufacturing Logic Technology Featuring Novel 45nm Gate Length Strained Silicon CMOS Transistors,” IEDM (2003) pp. 978-980.
Lee, B.H., et al., “Performance Enhancement on Sub-70nm Strained Silicon SOI MOSFETs on Ultra-thin Thermally Mixed Strained Silicon/SiGe on Insulator (TM-SGOI) Substrate with Raised S/D,” IEDM (2002) pp. 946-948.
Mizuno, T., et al., “High-Performance Strained-SOI CMOS Devices Using Thin Film SiGe-on-Insulator Technology,” IEEE Transactions on Electron Devices, vol. 50, No. 4 (Apr. 2003) pp. 988-994.
Shimizu, A., et al., “Local Mechanical-Stress Control (LMC): A New Technique for CMOS-Performance Enhancement,” International Electron Devices Meeting (2001) pp. 433-436.
Tezuka, T., et al., “A Novel Fabrication Technique of Ultrathin and Relaxed SiGe Buffer Layers with High Ge Fraction for Sub-100 nm Strained Silicon-on-Insulator MOSFETs,” Jpn. J. Appl. Phys., vol. 40 (Apr. 2001) pp. 2866-2874.
Chang Chih-Chien
Lee Tze-Liang
Lin Li-Te S.
Slater & Matsil L.L.P.
Taiwan Semiconductor Manufacturing Company , Ltd.
Wilson Allan R.
LandOfFree
Embedded SiGe stressor with tensile strain for NMOS current... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Embedded SiGe stressor with tensile strain for NMOS current..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Embedded SiGe stressor with tensile strain for NMOS current... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4127675