Embedded bit line structure, field effect transistor...

Details Embedded bit line structure, field effect transistor... Embedded bit line structure, field effect transistor...

2011-05-24

2011-05-24

Ho, Tu-Tu V (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S347000, C257S349000, C257SE27112, C257SE29262, C438S212000

Reexamination Certificate

active

07948027

ABSTRACT:
An embedded bit line structure, in which, a substrate includes an insulator layer having an original top surface and a semiconductor layer on the original top surface of the insulator layer, and a bit line is disposed within the lower portion of the trench along one side of an active area. The bit line includes a first portion and a second portion. The first portion is located within the insulator layer and below the original top surface of the insulator layer. The second portion is disposed on the first portion to electrically connect the semiconductor layer of the active area. An insulator liner is disposed on the first portion of the bit line and between the second portion of the bit line and the semiconductor layer of the substrate opposite the active area for isolation. An STI is disposed within the trench to surround the active area for isolation.

REFERENCES:
patent: 7518182 (2009-04-01), Abbott et al.
Kazumi Inoh, et al., “FBC (Floating Body Cell) for Embedded DRAM on SOI”, 2003 Symposium on VLSI Technology Digest of Technical Papers, 2003.
Tomoaki Shino, et al., “Highly Scalable FBC (Floating Body Cell) with 25nm Box Structure for Embedded DRAM Applications”, 2004 Symposium on VLSI Technology Digest of Technical Papers, 2004, pp. 132-133, IEEE.

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