Semiconductor device having laminated structure

Details Semiconductor device having laminated structure Semiconductor device having laminated structure

2011-01-25

2011-01-25

Smith, Bradley K (Department: 2894)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S680000, C257SE33056, C257S700000

Reexamination Certificate

active

07875980

ABSTRACT:
A technique for reducing the size of a semiconductor device is provided. A semiconductor device comprises a base, a semiconductor chip, a chip component, an insulating base, a wiring pattern, a via plug, an external lead-out electrode, a recess, and a resin. The insulating base has a multi-layer structure formed by laminating a plurality of insulator films. The semiconductor chip and the chip component are mounted on the base and embedded in the insulating base. A recess is formed on the surface of the semiconductor device and reaches down to any of wiring conductor layers. The semiconductor chip and the chip component are mounted on the recess.

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Japanese Notification of Reason(s) for Refusal, with English translation thereof, issued in Patent Application No. JP 2004-253998 dated on Jul. 8, 2008.

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