Elimination of the fast-erase phenomena in flash memory

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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C438S197000, C438S381000

Reexamination Certificate

active

07045419

ABSTRACT:
A method of forming a semiconductor device that includes providing a semiconductor substrate, forming a first insulating layer over the semiconductor substrate, forming a floating gate over the first insulating layer with a reaction gas, wherein the floating gate comprises a microcrystalline material having a grain size of about 50–300 Å, forming a second insulating layer over the floating gate, and forming a control gate over the second insulating layer.

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Seiichi Mori et al., “Polyoxide Thinning Limitation and Superior ONO Interpoly Dielectric for Nonvolatile Memory Devices”, IEEE Transactions on Electron Devices, vol. 38, No. 2, Feb. 1991, pp. 270-277.
Seiichi Mori et al., “ONO Inter-Poly Dielectric Scaling for Nonvolatile Memory Applications”, IEEE Transactions on Electron Devices, vol. 38, No. 2, Feb. 1991, pp. 386-391.

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