Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1998-04-16
2000-05-02
Hardy, David
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438261, 438257, 438618, 438620, 438631, 257315, 257316, H01L 21336
Patent
active
060571934
ABSTRACT:
A method (200) of forming a NAND type flash memory device includes the steps of forming an oxide layer (202) over a substrate (102) and forming a first conductive layer (106) over the oxide layer. The first conductive layer (106) is etched to form a gate structure (107) in a select gate transistor region (105) and a floating gate structure (106a, 106b) in a memory cell region (111). A first insulating layer (110) is then formed over the memory cell region (111) and a second conductive layer (112, 118) is formed over the first insulating layer (110). A word line (122) is patterned in the memory cell region (111) to form a control gate region and source and drain regions (130, 132) are formed in the substrate (102) in a region adjacent the word line (122) and in a region adjacent the gate structure (107). A second insulating layer (140) is formed over both the select gate transistor region (105) and the memory cell region (111) and first and second contact openings are formed in the second insulating layer (140) down to the gate structure (107) and the control gate region, wherein a depth (X) through the second insulating layer (140) down to the gate structure (107) and down to the control gate region are approximately the same, thereby eliminating a substantial overetch of the gate structure contact opening.
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International Search Report, International Application No. PCT/US99/03043, International Filing Date Nov. 2, 1999 mailed Jun. 9, 1999.
Fang Hao
Higashitani Masaaki
Wang John Jianshi
Advanced Micro Devices , Inc.
Fujitsu AMD Semiconductor Limited
Fujitsu Limited
Hardy David
Richards N. Drew
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