Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Patent
1998-03-03
2000-08-29
Utech, Benjamin L.
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
701743, H01L 2170
Patent
active
061108332
ABSTRACT:
A method for fabricating a first memory cell and a second memory cell electrically isolated from each other is provided. A first polysilicon (poly I) layer is formed on an oxide coated substrate. Then, a sacrificial oxide layer and nitride layer are formed for masking the poly I layer. At least a portion of the masking layer is etched to pattern the first memory cell and the second memory cell and an unmasked portion therebetween. The unmasked portion of the poly I layer is transformed into an insulator via thermal oxidation such that the insulator separates a floating gate of the first memory cell from a floating gate of the second memory cell. The insulator is etched so as to form a gap having gradually sloping sidewalls between a floating gate of the first memory cell and a floating gate of the second memory cell, the gap isolating the floating gate of the first memory cell from the floating gate of the second memory cell. Thereafter, an interpoly dielectric layer and a second polysilicon (poly II) layer are formed substantially free of abrupt changes in step height.
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Chan Maria C.
Early Kathleen R.
Templeton Michael K.
Tripsas Nicholas H.
Advanced Micro Devices , Inc.
Brown Charlotte A.
Utech Benjamin L.
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