Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-11-02
2001-08-21
Booth, Richard (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
Reexamination Certificate
active
06277690
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the manufacture of high density, high performance semiconductor devices. More specifically, this invention relates to the manufacture of high density, high performance semiconductor devices utilizing a reduced number of steps during the manufacturing process.
2. Discussion of the Related Art
In order to remain competitive, a semiconductor manufacture must continuously increase the performance of the semiconductor integrated circuits being manufactured and at the same time, reduce the cost of the semiconductor integrated circuits. Part of the increase in performance and the reduction in cost of the semiconductor integrated circuits is accomplished by shrinking the device dimensions and by increasing the number of devices per unit area on an integrated circuit chip. Another part of reducing the cost of a semiconductor chip is to increase the throughput of the fabrication facility (the “fab”).
A single semiconductor chip requires numerous process steps such as oxidation, etching, metallization and wet chemical cleaning. Some of these process steps involve placing the wafer on which the semiconductor chips are being manufactured into different tools during the manufacturing process. As can be appreciated, a reduction in the number of process steps in which the semiconductor wafers must be moved from one tool to another can be a major increase in the throughput of the fabrication facility as well as a major decrease in the cost of manufacturing the chips on the semiconductor wafer.
Therefore, what is needed are methods of reducing the number of processing steps necessary to manufacture semiconductor wafers on which semiconductor integrated chips are manufactured.
SUMMARY OF THE INVENTION
According to the present invention, the foregoing and other objects and advantages are obtained by a method of manufacturing a semiconductor memory device that reduces the number of manufacturing steps required to manufacture the device.
In accordance with an aspect of the invention, the method includes the following sequence of steps: forming gate structures on a semiconductor substrate in regions in which core, n-channel and p-channel transistors are to be formed in the semiconductor substrate; forming resist spacers on the n-channel transistor gate and implanting the core transistor region and n-channel transistor region with an Mdd implant; implanting the p-channel transistor regions with a PLdd implant; implanting the n-channel transistor regions with an NLdd implant; forming sidewall spacers on the gate structures; implanting the p-channel transistor regions with a P
+
implant; and forming N
+
and P
+
contacts. The combination of this sequence of steps with the formation of the resist spacers allow the following standard process steps to be skipped: the formation of the N
+
implant resist coat step; the N
+
implant masking step; and the N
+
implant step.
The described method thus reduces the number of manufacturing steps required to manufacture a semiconductor device.
The present invention is better understood upon consideration of the detailed description below, in conjunction with the accompanying drawings. As will become readily apparent to those skilled in the art from the following description, there is shown and described an embodiment of this invention simply by way of illustration of the best mode to carry out the invention. As will be realized, the invention is capable of other embodiments and its several details are capable of modifications in various obvious aspects, all without departing from the scope of the invention. Accordingly, the drawings and detailed description will be regarded as illustrative in nature and not as restrictive.
REFERENCES:
patent: 5183773 (1993-02-01), Miyata
patent: 5292681 (1994-03-01), Lee et al.
patent: 5933730 (1999-08-01), Sun et al.
patent: 6004843 (1999-12-01), Huang
patent: 6037222 (2000-03-01), Huang et al.
patent: 6069033 (2000-05-01), Verhaar et al.
Hamilton Darlene
Toyoshiba Len
Advanced Micro Devices , Inc.
Booth Richard
Nelson H. Donald
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