Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
1999-07-20
2001-06-26
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
Reexamination Certificate
active
06251791
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The proposed invention relates to a method for eliminating the etching microloading effect, and more particularly to a method of forming wide and narrow trenches with same depth simultaneously.
2. Description of the Prior Art
In most of practical semiconductor fabrications, there are a plurality of elements in a layer of an integrated circuit and each element has individual shape and size. When an etching process is used to form these elements, fabrication of these elements comprises following steps:
First, a photo-resist is formed on the layer with many openings where each opening corresponds to a specific element.
Second, effecting an etching process to etch the layer and to form a plurality of trenches in said layer, where each trench corresponds to a specific element.
Third, performing following fabrication such as depositing to completely form these elements.
It should be noted that because the distance between any two adjacent layers is fixed in a multi-layer integrated circuit, depth of any the underlying layer maybe are destroyed by these trenches. This is a primary restriction of formation of these trenches.
No matter how, the primary restriction is violated by the key technical issue for the plasma etching process: the etching microloading effect. The etching microloading effect means that when ions do not totally vertically collide to a substrate, the colliding probability of a wide trench is higher that the colliding probability of a narrow trench, then both etching rate and depth of any trench are different to each other.
Refer to
FIG. 1A
where the mechanism of the etching microloading effect is briefly explained in the provided example. As
FIG. 1A
shows, dielectric layer
10
is formed on substrate
11
, where substrate
11
comprises metal oxide semiconductor transistor and isolation. And when integrated circuit is a multi-layer integrated circuit, substrate
11
further comprises a multi-layer trench with a plurality of dielectric layers, a plurality of contacts and a plurality of interconnects. On the surface of dielectric layer
10
, photo-resist
12
is formed with first opening
13
and second opening
14
, where width (W
1
) of first opening
13
is smaller than width (W
2
) of second opening
14
.
Owing to the ability of available plasma reactor, it is obvious that during an etching process, ions
15
do not totally vertically collide dielectric
10
. Therefore, the wider width of second opening
14
increases the probability that inclined incident ions
15
collide to dielectric layer
10
. And the result is the etching rate is larger in second opening
14
but is lower in first opening
13
. The phenomenon is known as the etching microloading effect.
Consequently, the result of the etching microloading effect is shown in FIG.
1
B. Obviously, first trench
16
that corresponds to first opening
13
is shallow and second trench
17
that corresponds to second opening
14
is deep. Therefore, either second trench
17
just touches substrate
11
but first trench
16
does not touch substrate
11
, or first trench
16
just touches substrate
11
but second trench
17
penetrates substrate
11
and maybe be destroy some structure inside substrate
11
.
According to previous discussion, it is obvious that etching microloading effect is serious and it is desired to develop a method for forming a plurality trenches with same depth but individual width.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an effective and manufacturable method for forming both wide and narrow trenches with same depth simultaneously.
Another object of the present invention is to provide a method of forming different trenches with same depth by pre-forming a coating layer on a photo-resist.
A further object of the present invention is to provide a method that not only eliminates disadvantages of the etching microloading but also keep throughput in a high level.
In order to realize these objects of this invention, a method for eliminating the etching microloading effect is proposed. In the method, a coating layer is deposited on a photo-resist that covers a substrate before an etching process is perform. Because step coverage of the coating layer is limited by the aspect of opening of photo-resist, indisputably, depth of coating layer on bottom of a narrow opening is smaller than depth of coating layer on bottom of a wide opening. By the way, during following etching process, although etching microloading effect induces etching rate is higher in the wide opening and is lower in the narrow opening, but the thicker coating layer on bottom of the wide opening also requires larger etching time than the narrow opening. Then it is possible to form wide trench and narrow trench in the dielectric layer with same depth simultaneously.
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patent: 4838978 (1989-06-01), Sekine et al.
patent: 5236863 (1993-08-01), Iranmensh
patent: 5302882 (1994-04-01), Miller
patent: 5354421 (1994-10-01), Tatsumi et al.
patent: 5413966 (1995-05-01), Schoenborn
patent: 5670401 (1997-09-01), Tseng
patent: 5729563 (1998-03-01), Wang et al.
patent: 5811357 (1998-09-01), Armacost et al.
patent: 5814547 (1998-09-01), Chang
Tsai Ming-Huan
Yang Chan-Lon
Umez-Eronini Lynette T.
United Microelectronics Corp.
Utech Benjamin L.
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