Eliminate broken line damage of copper after CMP

Details Eliminate broken line damage of copper after CMP Eliminate broken line damage of copper after CMP

2001-11-20

2004-05-18

Hail, III, Joseph J. (Department: 3723)

Abrading

Precision device or process - or with condition responsive...

With indicating

C451S036000, C438S692000

Reexamination Certificate

active

06736701

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method to prevent damage to copper lines during the process of polishing copper lines.
(2) Description of the Prior Art
The present invention relates to the creation of conductive lines and vias that provide the interconnection of integrated circuits in semiconductor devices and/or the interconnections in a multilayer substrate on which semiconductor device(s) are mounted. The present invention specifically relates to the fabrication of conductive lines and vias by a process known as damascene. Damascene is an interconnection fabrication process in which grooves are formed in an insulating layer and filled with metal to form the conductive lines. Dual damascene is a multi-level interconnection process in which, in-addition to forming the grooves of single damascene, conductive via openings also are formed. Copper damascene wiring is one of the most promising technologies to reduce RC delay as well as to implement the shrinkage of interconnect structures. For this, Chemical Mechanical Polishing (CMP) of inlaid copper is required to form the copper wiring. One of the major problems that is encountered when polishing inlaid copper patterns is the damage that is caused on the copper trench as a consequence of the polishing process. The invention addresses this concern and provides a novel method for damascene trench planarization by CMP processes.
Chemical Mechanical Polishing is a method of polishing materials, such as semiconductor substrates, to a high degree of planarity and uniformity. The process is used to planarize semiconductor slices prior to the fabrication of semiconductor circuitry thereon, and is also used to remove high elevation features created during the fabrication of the microelectronic circuitry on the substrate. One typical chemical mechanical polishing process uses a large polishing pad that is located on a rotating platen against which a substrate is positioned for polishing, and a positioning member which positions and biases the substrate on the rotating polishing pad. Chemical slurry, which may also include abrasive materials, is maintained on the polishing pad to modify the polishing characteristics of the polishing pad in order to enhance the polishing of the substrate.
While copper has become important for the creation of multilevel interconnections, copper lines frequently show damage after CMP and clean. This in turn causes problems with planarization of subsequent layers that are deposited over the copper lines since these layers may now be deposited on a surface of poor planarity. Isolated copper lines or copper lines that are adjacent to open fields are susceptible to damage. While the root causes for these damages are at this time not clearly understood, poor copper gap fill together with subsequent problems of etching and planarization are suspected. Where over-polish is required, the problem of damaged copper lines becomes even more severe.
During the Chemical Mechanical Planarization (CMP) process, semiconductor substrates are rotated, face down, against a polishing pad in the presence of abrasive slurry. Most commonly, the layer to be planarized is an electrical insulating layer overlaying active circuit devices. As the substrate is rotated against the polishing pad, the abrasive force grinds away the surface of the insulating layer. Additionally, chemical compounds within the slurry undergo a chemical reaction with the components of the insulating layer to enhance the rate of removal. By carefully selecting the chemical components of the slurry, the polishing process can be made more selective to one type of material than to another. For example, in the presence of potassium hydroxide, silicon dioxide is removed at a faster rate than silicon nitride. The ability to control the selectivity of a CMP process has led to its increased use in the fabrication of complex integrated circuits.
It is well known in the art that, in the evolution of integrated circuit chips, the process of scaling down feature sizes results in making device performance more heavily dependent on the interconnections between devices.
In addition, the area required to route the interconnect lines becomes large relative to the area occupied by the devices. This normally leads to integrated circuit chips with multilevel interconnect lines. The chips are often mounted on multi-chip modules that contain buried wiring patterns to conduct electrical signals between the various chips. These modules usually contain multiple layers of interconnect metalization separated by alternating layers of an isolating dielectric.
Any conductor material to be used in a multilevel interconnect has to satisfy certain essential requirements such the underlying substrate material, stability (both electrical and mechanical) and ease of processing.
Copper is often preferred due to its low resistivity, high electromigration resistance and stress voiding resistance. Copper unfortunately suffers from high diffusivity in common insulating materials such as silicon oxide and oxygen-containing polymers. For instance, copper tends to diffuse into polyimide during high temperature processing of the polyimide. This causes severe corrosion of the copper and the polyimide due to the copper combining with oxygen in the polyimide. This corrosion may result in loss of adhesion, delamination, voids, and ultimately a catastrophic failure of the component. A copper diffusion barrier is therefore often required.
Copper is typically very difficult to process using RIE technology as a consequence of which a method that uses CMP for copper wire formation offers significant advantages. To polish a buried copper wiring formation at a high polishing rate and without damaging the surface, the copper etch rate must be raised by increasing the amount of the component that is responsible for copper etching that is contained in the polishing slurry. If the component continues to be increased, the etching will occur isotropically whereby buried copper is etched away, causing dishing in the wiring. Thus, it is difficult to form a highly reliable LSI wiring made of copper.
FIG. 1
shows a Prior Art CMP apparatus. A polishing pad
20
is attached to a circular polishing table
22
that rotates in a direction indicated by arrow
24
at a rate in the order of 1 to 100 RPM. A wafer carrier
26
is used to hold wafer
18
facedown against the polishing pad
20
. The wafer
18
is held in place by applying a vacuum to the backside of the wafer (not shown). The wafer
18
can also be attached to the wafer carrier
26
by the application of a substrate attachment film (not shown) to the lower surface of the wafer carrier
26
. The wafer carrier
26
also rotates as indicated by arrow
32
, usually in the same direction as the polishing table
22
, at a rate on the order of 1 to 100 RPM. Due to the rotation of the polishing table
22
, the wafer
18
traverses a circular polishing path over the polishing pad
20
. Slurry
23
is supplied to the surface of the wafer
18
that is being polished. A force
28
is also applied in the downward vertical direction against wafer
18
and presses the wafer
18
against the polishing pad
20
as it is being polished. The force
28
is typically in the order of 0 to 15 pounds per square inch and is applied by means of a shaft
30
that is attached to the back of wafer carrier
26
.
A typical CMP process involves the use of a polishing pad made from a synthetic fabric and a polishing slurry, which includes pH-balanced chemicals, such as sodium hydroxide, and silicon dioxide particles.
Abrasive interaction between the wafer and the polishing pad is created by the motion of the wafer against the polishing pad. The pH of the polishing slurry controls the chemical reactions, e.g. the oxidation of the chemicals that comprise an insulating layer of the wafer. The size of the silicon dioxide particles controls the physical abrasion of surface of the wafer.

Affiliated with

Also associated with

Rating

Eliminate broken line damage of copper after CMP does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Eliminate broken line damage of copper after CMP, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Eliminate broken line damage of copper after CMP will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3249298