Elevated transistor fabrication technique

Details Elevated transistor fabrication technique Elevated transistor fabrication technique

1997-06-11

1998-11-10

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438416, H01L 21336

Patent

active

058343504

ABSTRACT:
A second transistor is formed a spaced distance above a first transistor. An interlevel dielectric is first deposited upon the upper surface of the first semiconductor substrate and the first transistor. A second semiconductor substrate, preferably comprising polysilicon, is then formed into the interlevel dielectric. A second transistor is then formed on the upper surface of the second semiconductor substrate. The second transistor is a spaced distance above the first transistor. The two transistors are a lateral distance apart which is smaller than the distance that can be achieved by conventional fabrication of transistors on the upper surface of the wafer. Transistors are more closely packed which results in an increase in the number of devices produced per wafer.

REFERENCES:
patent: 3791024 (1974-02-01), Boleky, III
patent: 4868137 (1989-09-01), Kubota
patent: 5728619 (1998-03-01), Tsai et al.
patent: 5731217 (1998-03-01), Kadosh et al.

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