Elevated source/drain salicide CMOS technology

Details Elevated source/drain salicide CMOS technology Elevated source/drain salicide CMOS technology

1998-07-09

1999-11-30

Bowers, Charles

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438630, 438648, 438649, 148DIG147, 148305, H01L 21336

Patent

active

059941910

ABSTRACT:
Low resistivity metal silicide layers are formed on a gate electrode and source/drain regions at an optimum thickness for reducing parasitic series resistances with an attendant consumption of silicon from the gate electrode and source/drain regions. Consumed silicon from the gate electrode and source/drain regions is then replaced employing metal induced crystallization, thereby avoiding a high leakage current. Embodiments include depositing a layer of amorphous silicon on the metal silicide layers and heating at a temperature of about 400.degree. C. to about 600.degree. C. initiating metal induced crystallization, thereby causing the metal silicide layers grow upwardly as silicon in the underlying gate electrode and source/drain regions is replaced.

REFERENCES:
patent: 4835112 (1989-05-01), Pfiester et al.
patent: 5409853 (1995-04-01), Yu
patent: 5589417 (1996-12-01), Jeng
patent: 5744395 (1998-04-01), Shue et al.
patent: 5913139 (1999-06-01), Hashimoto et al.
"Low Temperature Poly-Si Thin-Film Transistor Fabrication by Metal-Induced Lateral Crystallization"; Seok-Woon Lee and Seung-Ki Joo. IEEE Electron Device Letters, vol. 17, No.4, Apr. 1996, pp. 160-162.

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