Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2003-04-08
2004-11-23
Ho, Hoai (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S091000, C438S141000
Reexamination Certificate
active
06821831
ABSTRACT:
FIELD OF THE INVENTION
The field of this invention is design and fabrication of MOS transistors. More specifically it involves protection of double diffused MOS (DMOS) transistors from electrostatic discharge (ESD).
BACKGROUND OF THE INVENTION
DMOS transistors are used widely in both RF analog and mixed-signal integrated circuits (ICs), in dielectrically isolated ICs for power and high voltage applications, and as discrete devices. It is known that these devices, in common with many types of electronic components, are susceptible to electrostatic discharge (ESD). Sources of static discharge are common in the use environment, and also occur during transistor manufacture. The latter can be controlled, but managing static or other forms of high voltage to which electronic equipment is exposed during use of the equipment requires static protection that is built into the device itself. Thus, typical DMOS transistor circuits have electrical devices, typically diodes, incorporated into the integrated circuit package.
It is most convenient, and cost effective, to integrate the protection diode into the integrated circuit itself. See for example, U.S. Pat. Nos. 4,763,184, 5,463,520, and 5,304,839. The diode in these arrangements is isolated from the active circuit by a variety of p-n junction isolation techniques.
In the case of discrete DMOS devices, it is not desirable to add processing steps to integrate the ESD protection on the same chip as the discrete device. Accordingly, with many discrete devices with ESD protection, discrete ESD protection diodes, typically Zener diodes, are used. In these arrangements the Zener diode can be mounted on the same board as the device and can thus be made relatively small. However, the ESD protection device adds cost and assembly complexity as compared with an integrated ESD device.
As the lithography of the DMOS devices shrinks, and the gate dielectric becomes thinner, effective ESD, especially in an integrated form, becomes more demanding for RF applications. Further, restrictions on the ESD protection scheme of the DMOS is imposed because of the high frequency operation of the device. The main ESD protection needed is primarily between the gate and the source terminals (the input in an RF amplifier). Adding any type of ESD structure should not increase appreciably the capavitance (gate to source, or input capacitance) otherwise the RF characteristics of the amplifier will be degraded. Thus, integrating the ESD protection to control the parasitics is particularly important for RF applications. From this discussion it should be evident that there remains a need for better techniques to protect sensitive devices against accidental high voltage discharge.
STATEMENT OF THE INVENTION
I have developed an improved MOS transistor device design and fabrication method that addresses ESD protection. It is a fully integrated design with improved isolation between the ESD device and the integrated circuit. In the preferred embodiment the MOS transistor is a DMOS device. The ESD protection method of the invention relies on standard IC production steps in which a Zener diode and the equivalent circuit structure of
FIG. 1
, are produced in the IC substrate. The Zener diode, and the other elements, are formed using the same process steps used to fabricate the DMOS devices. A heavily doped guard ring structure is formed around the p-n junction of the Zener diode. A V-groove or trench is etched around the p-n junction and guard ring down to the buried source region and the V-groove or trench is metallized to short the guard ring to the source. This structure provides effective ESD isolation from the DMOS IC devices, with enhanced current capacity in the Zener diode due to the low resistance (metallized) current path between the guard ring and ground. The structure is completely process compatible with the process design for the DMOS devices.
REFERENCES:
patent: 5138422 (1992-08-01), Fujii et al.
patent: 5535231 (1996-07-01), Lee et al.
patent: 5602046 (1997-02-01), Calafut et al.
patent: 5710072 (1998-01-01), Krautschneider et al.
patent: 6657256 (2003-12-01), Hshieh et al.
Agere Systems Inc.
Ho Hoai
Le Thao P.
Wilde P. V. D.
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