Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-09-10
2003-04-15
Zarabian, Amir (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S301000, C438S303000, C438S305000, C438S479000, C438S480000, C438S481000, C438S766000, C438S607000
Reexamination Certificate
active
06548360
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates in general to an electrostatic discharge protection (ESD) apparatus. More particularly, this invention relates to the formation of an ESD apparatus with silicon control rectifier (SCR) using a silicon on insulator (SOI) CMOS technique and a selective epitaxial growth (SEG) technique.
2. Description of the Related Art
During the fabrication process of an integrated circuit (IC), such as a dynamic random access memory (DRAM) or a static random access memory (SRAM), or after the fabrication process of a chip is completed, electrostatic discharge is a common cause of damage to the integrated circuit. For example, when one walks on carpet in high relative humidity (HR), electrostatic voltage ranging from several hundred to several thousand volts can be carried. When the relative humidity is low, the electrostatic voltage can be more than ten thousand volts. If such electrostatic voltage is applied to he chips, several kinds of electrostatic discharge apparatus have to be employed to avoid damaging the chips. A conventional mechanism for electrostatic discharge protection is to form an on-chip electrostatic discharge circuit between each pad and the internal circuit.
FIG. 1
illustrates a conventional electrostatic discharge protection circuit with silicon control rectifier. Near the surface of an N-well
10
, two P-regions
12
,
14
are formed as a drain region and a source region. On the N-well
10
between the drain region
12
and the source region
14
, a P
+
region
16
is formed as a gate. An N region
18
is formed adjacent to the P region
14
. Thus constructed, a PNPN silicon control rectifier structure is formed with the sequential arrangement of P region
12
, N-well
10
, P region
14
and N region
18
.
The above circuit is formed in a way of bulk CMOS that results in a very poor heat dissipation effect. When a large current flows through, the device is easily blown. With the development of sub-micron fabrication techniques, the SOI COMS technique is now commonly used to enhance the operation speed and to obtain lower power consumption and a lower leakage current. The adapted theory is to add an insulation layer under and near the substrate surface, so as to isolate the substrate surface of the CMOS from the silicon bulk. Thus, the latch up between the source region and the substrate and between the well and substrate can be prevented. However, the above electrostatic discharge protection structure cannot employ the SOI CMOS technique.
SUMMARY OF THE INVENTION
The invention provides an electrostatic discharge protection circuit with a silicon control rectifier. Using selective epitaxial growth, the resistance of the source/drain region can be reduced, and the SOI CMOS technique can be employed.
The electrostatic discharge protection apparatus comprises a bottom layer, a P-well, a first source/drain region, a second source/drain region, a gate, a selective epixatial growth region and an N
+
region. The P-well is located on the bottom layer, while the first and the second source/drain regions are formed within the P-well. The gate is formed on a part of the first source/drain region, a part of the P-well and a part of the second source/drain region. The selective epitaxial growth region is formed on the first source/drain region and next to the gate. The N
+
region is formed on the bottom layer with its bottom portion adjacent to the P-well, and its top portion adjacent to the gate. Due to the formations of the selective epitaxial growth region and the N
+
region, the junction depth is deepened to effectively reduce the resistance and improve the heat dissipation.
The bottom layer is formed using SOI technique to include a substrate layer as a lower portion and an insulation layer on the substrate layer. The substrate layer can be a P-type substrate material, and the insulation layer can be made of silicon dioxide. In addition, the gate further comprises a pair of spacers on the sidewalls thereon. The spacers are respectively adjacent to the selective epitaxial growth region and the N
+
region. A P region is typically selected for the selective epitaxial growth region. N regions with a lower dopant concentration than the N
+
region are typically selected for the first and the second source/drain regions.
The invention further provides a method for fabricating an electrostatic discharge protection apparatus with a silicon control recrifier. A substrate layer is provided. An insulation layer is provided on the substrate layer. A P-well is formed on the insulation layer. A gate, a first source/drain region and a second source/drain region are formed on the P-well. The first and the second source/drain regions are formed in the P-well at two sides of the gate. A selective epitaxial growth region is further formed on the first source/drain region. An N
+
region is formed on the insulation layer. The N
+
region is downwardly connected to the P-well, the second source/drain region and the gate.
Similarly, the above substrate layer can be formed of a P-type substrate, and the insulation layer may comprise silicon dioxide to construct the SOI CMOS. In addition, the gate further comprises a pair of spacers on a pair of sidewalls to connect with the selective epitaxial growth region and the N
+
region. A P-type region is typically used as the selective epitaxial growth region. An N-type region with a dopant concentration lower than that of the N
+
region is used for forming the first and the second source/drain regions.
Both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention as claimed.
REFERENCES:
patent: 5807771 (1998-09-01), Vu et al.
patent: 6190977 (2001-02-01), Wu
patent: 6303450 (2001-10-01), Park et al.
patent: 6342421 (2002-01-01), Mitani et al.
patent: 6391692 (2002-05-01), Nakamura
Huang Chiu-Tsung
Liu Lu-Min
Yeh Wen-Kuan
J.C. Patents
Thomas Toniae M.
United Microelectronics Corp.
Zarabian Amir
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