Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-04-12
2002-11-12
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S288000
Reexamination Certificate
active
06479871
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention lies in the integrated technology field and relates, more specifically, to an ESD protective circuit for an integrated circuit, which is integrated in a semiconductor substrate of the integrated circuit, having a lateral pnpn “latch-up” protective structure formed by a first region, which is doped with a first doping type, is arranged in a well doped oppositely, with a second doping type, and is provided with a first connection electrode, the well being inserted into the semiconductor substrate doped with the first doping type, and also by a second region, which is doped with the second doping type, is arranged outside the well in the semiconductor substrate and is provided with a second connection electrode, and having a highly doped zone of the second doping type, which is arranged on the well boundary, at the same time partly overlapping the well, along that section of the periphery of the well which runs between the two regions.
An ESD protective circuit of that type is disclosed in the reference book by Amerasekera and Duvvury, “ESD in Silicon Integrated Circuits”, John Wiley and Sons, Chichester (1995).
Integrated circuits, primarily the sensitive circuits using complementary MOS technology (CMOS), are often intended to be protected against damage which can be caused by an electrostatic discharge (ESD). An ESD event can result in a voltage breakdown through a dielectric that isolates two surfaces, that is to say ultimately a short circuit, which may lead to damage for example in oxide layers or on interconnects or connections of the integrated circuit. The electrostatic charging of the circuit that precedes this sudden discharge is usually brought about through contact between the circuit and an electrically charged human body or a charged machine.
In order to afford protection against such ESD events, it is customary to integrate protective circuits on the semiconductor substrate of the circuit to be protected, which, when a hazardous discharge current and/or a discharge voltage occurs, are activated, assume a low-impedance state and draw off the discharge current at least to an extent such that the sensitive regions of the circuit to be protected remain safe. So far, circuits having lateral pnpn “latch-up” structures have proved to be the most effective ESD protection.
The “latch-up” effect, which has been known per se for a fairly long time, was originally perceived only as an undesirable error source in CMOS circuits. Almost all CMOS circuits have a lateral and a vertical parasitic bipolar transistor which together form a four-layer diode pnpn, comparable to a thyristor. The four-layer structure can be triggered in the event of interference of the applied supply voltage. This transition from the normal state of the pnpn structure to a highly conductive state is referred to as “latch-up”. The integrated circuit can be thermally overloaded by the current path formed in an undesired manner between the transistor connections in this context.
A structure which is similar but is produced in a desired manner and in addition to the actual integrated circuit and is based on elements arranged laterally in the substrate is currently used, as already mentioned, as ESD protection and is described in detail in sections 4.2.4 to 4.3.1 of the aforementioned reference book. This known latch-up protective structure (Lateral Silicon Controlled Rectifier, LSCR) or its modified embodiment (MLSCR) that is also described therein will now be explained, in order to provide a better understanding of the invention, in connection with
FIG. 3
(cf.
FIGS. 4.35
and
4
.
31
in Amerasekera and Duvvury, supra).
FIG. 3A
shows a schematic cross-sectional view of a prior art MLSCR ESD protective structure. There, an n-conducting well
2
is inserted into a weekly p-doped substrate
1
. A highly p-doped region
3
and, in order to connect the n-type well
2
to the supply voltage, a highly n-doped region
4
are produced in the n-type well
2
. A further highly n-doped region
5
, which is connected to ground, is produced outside the n-type well
2
. This configuration already produces a lateral pnpn structure:
Region
3
, n-type well
2
, p-type substrate
1
, region
5
,
which forms the basic LSCR protective structure. What is crucial for the triggering voltage of the pnpn protective structure is the pn junction between the p-type substrate
1
and the n-type well
2
. A triggering voltage of about 50 V or less results for contemporary typical CMOS process parameters.
With the ever greater miniaturization of the structures on the semiconductor chips and the associated danger caused even by smaller voltages, there is a need for ESD protective circuits which react even to low voltages, for example below 50 V. In order to reduce the triggering voltage, the cited literature therefore proposes additionally arranging the highly n-doped zone
6
—illustrated in FIG.
3
A—above the well boundary between the n-type well
2
and the p-type substrate
1
. By virtue of this measure, the triggering voltage of the thus modified LSCR structure (MLSCR) in typical 0.8 &mgr;m CMOS processes is virtually halved and the parasitic capacitance is increased. The highly doped n-type zone
6
proposed is embodied as strips on the well boundary.
FIG. 3B
shows the layout of the circuit of
FIG. 3A
in a schematic view from above. The regions
3
and
4
situated within the n-type well
2
, and the region
5
situated laterally outside the n-type well
2
are shown. The strip-shaped highly doped n-type zone
6
on that section of the periphery
7
of the n-type well
2
which runs between the regions
3
and
5
is intended to have the effect that the lateral latch-up structure used as protective structure triggers both statically and dynamically in the case of an ESD event at a lower voltage than previously, and thus also sooner than other, unintentional parasitic latch-up structures within the integrated circuit, in order thus to avoid a failure of the circuit due to interconnects melting, increased leakage currents, and the like.
Although the use of the MLSCR achieves the lowering of the triggering voltage that is sought, it is also known from the cited literature and it has been confirmed in practical tests that the lowering of the triggering voltage with the aid of the n-type zone
6
is accompanied by the disadvantage of a higher on resistance of the pnpn protective structure after triggering. The consequence of this, for example for a chip which, with the LSCR, exhibited failures above 2 kV (ESD test according to the human body model), is that failures occur at as little as 1.5 kV when the MLSCR is used. In accordance with the cited literature, the increased on resistance is brought about precisely by the n-type diffusion strip
6
which is used to lower the triggering voltage and lies directly in the low-impedance (after triggering) path of the pnpn structure.
SUMMARY OF THE INVENTION
The object of the present invention is to provide an ESD protective circuit which overcomes the above-noted deficiencies and disadvantages of the prior art devices and methods of this general kind, and which results in a low triggering voltage, but without an increased on resistance.
With the above and other objects in view there is provided, in accordance with the invention, an ESD protective circuit for an integrated circuit in a semiconductor substrate having a doping of a first doping type, comprising:
a lateral pnpn “latch-up” protective structure formed by
a first region with a doping of a first doping type arranged in a well formed in the semiconductor substrate and having a doping of a second doping type opposite the first doping type, and formed with a first connection electrode;
a second region with a doping of the second doping type arranged outside the well in the semiconductor substrate, and formed with a second connection electrode; and
a highly doped zone formed of a plurality of mutually spaced-apart pads with a doping of the second doping type, the pads b
Peters Christian
Uffmann Dirk
Viehmann Hans-Heinrich
Flynn Nathan J.
Greenberg Laurence A.
Infineon - Technologies AG
Locher Ralph E.
Quinto Kevin
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