Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-07-25
2002-09-17
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S202000, C438S209000, C438S231000, 43, 43
Reexamination Certificate
active
06451655
ABSTRACT:
TECHNICAL FIELD
This invention relates to an electronic device monolithically integrated on a semiconductor, having a first power region and at least a second region, as well as an isolation structure of limited planar size.
More specifically, the invention relates to a monolithic semiconductor device, wherein P/N junctions are adapted to sustain high operating voltages; an example of these would be a base-collector junction of an NPN bipolar transistor.
The invention further relates to a method of manufacturing the device with the isolation structure of limited planar size.
The invention relates, particularly but not exclusively, to a structure of limited planar size functioning as an interface structure for a VIPOWER (Vertical Intelligent POWER) type of power structure, and the description to follow will make reference to this field of application for convenience of illustration only.
BACKGROUND OF THE INVENTION
As is known, VIPOWER structures normally comprise a HV power region and an LV drive region, both integrated in the same chip simultaneously, as shown schematically in FIG.
1
. In particular, the wells A represent wells intended for accommodating a range of different components which may be of the bipolar or the MOS type. N-doped wells A will be assumed hereinafter by way of example.
The wells A are surrounded by regions B with the opposite conductivity—of the P type in this case—such that they are isolated electrically from one another within the LV drive region and from the HV power region, in a condition of reverse bias of the junctions that they define in combination with the wells A.
It should be noted that the following considerations about isolation would equally apply to integrated structures having first and second power regions.
In VIPOWER structures, the isolation of the devices which form the drive circuitry and are accommodated in the LV region is obtained by the junction isolation technique.
The HV region and LV region are separated by an interface region, referenced C. This interface region C provides electrical and structural isolation between the LV and HV regions.
Similar as other parts of a VIPOWER structure, it comprises two epitaxial layers, referenced EPI
1
and EPI
2
, for forming the buried layers.
The regions referenced B are doped regions with a P-type species, whereas the interface region C is doped with an N-type species. The lateral sequence of the regions B-C-B originates a PNP parasitic component whose electrical effect may harm the adjacent components and should, therefore, be minimized. To attenuate or eliminate the effect of this parasitic component, measures of a structural nature must be taken in forming the interface regions C.
A known method for reducing the effect of the PNP parasitic component is that of placing the regions B at a suitable spacing from each other, thereby to lower the parasitic component gain. This results, however, in increased planar size of the device.
In a condition of high injection (Kirk Effect), the region B contained within the HV region can affect electrically the region B in the LV region. In particular, where a region B forms the base of a power component of the HV region, electric contact may be established with a region B of the P type contained in the LV drive region, resulting in alteration of the electrical characteristics of the device.
Thus, to further reduce the parasitic effects between the two regions, the interface region C should be enhanced with dopant of the N type at least at the surface thereof, so that the gain of the PNP parasitic component can be lowered in that area, and the expansion of the base region of the NPN power component by Kirk Effect be limited. The dopant enhancement of the interface region C is also effective to prevent “punch-through” from occurring between the wells in a condition of high-voltage reverse bias.
However, to avoid premature breakdown fields at the PIN junction formed by the high-voltage region B and the interface region C, the dopant enhanced portion of the region C should be prevented from coming in contact with the P-type dopant of the region B.
To confine the high voltage values to within the bulk region of the device, a field-plate metal layer is formed on top of the interface region C which is isolated from the surface silicon by an oxide region, thereby confining the high voltage to within the bulk area of the device.
In particular, a junction is obtained which has a P side and an N side (enhanced area), both heavily doped. At the photolithographic masking stage, a spacing is to be maintained between the N-enhanced region and the P-type wells to ensure that, after the dopant diffusion, the two heavily doped regions will not be contacting each other.
This arrangement, in combination with the P-type wells of the VIPOWER structures being fairly deep (no shallower than 15 microns), results in the interface region C being quite wide (usually no narrower than 40 microns).
Accordingly, prior approaches to forming interface isolation structures for power devices have resulted in the structures being of a large planar size. Thus, the dimensions of the interface region are the outcome of an extensive compromise, necessary for proper operation of the VIPOWER structures.
SUMMARY OF THE INVENTION
An embodiment of the present invention provides a device intended for working at a high voltage with isolation interface structures having such construction and operation features as to ensure proper performance of the device throughout its operational range, as well as reduced planar size, thereby overcoming the drawbacks with which prior art devices are still beset.
The device is an electronic power device with an isolation interface structure of limited planar size by having trench structures of substantial thickness formed in the silicon substrate and filled up with dielectric material.
The features and advantages of the electronic device according to the invention will become more clearly apparent from the following description of an embodiment thereof, given by way of non-limitative example with reference to the accompanying drawings.
REFERENCES:
patent: 3878551 (1975-04-01), Callahan, Jr.
patent: 4965215 (1990-10-01), Zambrano et al.
patent: 5308786 (1994-05-01), Lur et al.
patent: 5374583 (1994-12-01), Lur et al.
patent: 5408124 (1995-04-01), Palara
patent: 5650354 (1997-07-01), Himi et al.
patent: 5877050 (1999-03-01), Gardner et al.
patent: 6033947 (2000-03-01), Cacciola et al.
patent: 6040208 (2000-03-01), Honeycutt et al.
patent: 509183 (1992-10-01), None
patent: 735580 (1996-10-01), None
patent: 58161342 (1983-09-01), None
patent: 59112633 (1984-06-01), None
patent: 61110446 (1986-05-01), None
patent: 02068949 (1990-03-01), None
Cook Dale R.
Elms Richard
Jorgeson Lisa K.
Luu Pho M.
Seed IP Law Group PLLC
LandOfFree
Electronic power device monolithically integrated on a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Electronic power device monolithically integrated on a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Electronic power device monolithically integrated on a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2842420