Electronic package with offset reference plane cutout

Details Electronic package with offset reference plane cutout Electronic package with offset reference plane cutout

2002-07-23

2004-03-30

Clark, Jasmine (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

With window means

C257S691000, C257S693000, C257S662000, C257S663000, C257S664000

Reexamination Certificate

active

06713853

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to electronic packages. More particularly, the present invention relates to the design of electronic package reference planes utilized to support trace-to-terminal transitions.
BACKGROUND OF THE INVENTION
An electronic device package typically includes a substrate and an interconnect structure for routing signals from conductive traces or pads on the top surface of the substrate to connection terminals (e.g., solder balls) on the bottom surface of the substrate. For example, electronic chips and/or high speed signal connectors are often mounted in ball grid array (“BGA”) packages that can be easily attached to a printed circuit board (“PCB”) or an electronic component. A BGA package designed to accommodate a high speed signal typically includes conductive traces (e.g., a coplanar waveguide) formed on an upper surface of the BGA substrate and an interconnect structure that provides conductive paths from the conductive traces to the BGA solder balls located on the board-mounting substrate surface. The solder balls are attached to the substrate by way of capture pads formed at the bottom metal layer of the substrate. BGA packages are often utilized for high speed electronic devices, e.g., circuits that handle input and/or output signals having data rates of up to 40 Gbps. At high frequencies, the BGA capture pads and solder balls represent electrical discontinuities that limit the bandwidth of a signal propagating through the package. Indeed, in high speed applications, the trace-to-terminal transition can cause problematic impedance mismatching, high insertion loss, and high reflection loss.
BRIEF SUMMARY OF THE INVENTION
An electronic package according to a preferred embodiment utilizes a conductive reference plane having a cutout that is offset relative to the associated high speed signal solder ball. The offset cutout supports a longer portion of the high speed signal and also may reduce the capacitance load of the signal solder ball, which improves the impedance matching for high frequency signals propagating through the package. Consequently, the offset cutout improves the return loss, insertion loss, and bandwidth characteristics of the electronic package.
The above and other aspects of the present invention may be carried out in one form by a BGA package comprising a multilayer substrate having a mounting surface and one or more conductive layers, a signal solder ball attached to the multilayer substrate and coupled to a high speed signal trace formed at one of the conductive layers, and a reference plane formed at one of the conductive layers. The reference plane has a cutout region formed therein, where the cutout region has a lateral center point that is laterally offset relative to the lateral center point of the signal solder ball.


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patent: 6495911 (2002-12-01), Buffet et al.
patent: 2003/0015804 (2003-01-01), Staiculescu et al.

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