Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Flip chip
Reexamination Certificate
1999-10-29
2003-01-14
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Flip chip
C257S678000, C257S701000
Reexamination Certificate
active
06507116
ABSTRACT:
TECHNICAL FIELD
This invention relates generally to encapsulated semiconductor chips and more particularly to a semiconductor chip package, an electronic package, such as a flip chip package, having a thermally conductive member encapsulated with the semiconductor chip.
BACKGROUND OF THE INVENTION
A flip chip is a small semiconductor chip (chip) having terminations all on one side in the form of solder pads or bump contacts. Typically, the surface of the chip has been passivated or otherwise treated. The flip chip derives its name from the practice of flipping, or turning, the chip over after manufacture, prior to attaching the chip to a matching substrate.
Electronic packages, which include chips (including flip chips), usually require a cover, cap, or encapsulant of some type over the chip to protect it, and to provide a large flat surface for pick-and-place operations. However, any cover, cap, or encapsulant above the chip increases the thermal resistance path to an ambient environment and, hence, the operational temperature of the chip.
Various means have been used to mitigate the effects of such covers or caps. One approach has been to use a capped chip with a thin layer of a thermally conductive grease between the chip and the cap. However, it has been found that during thermal cycling, the grease has a tendency to be pumped, or displaced from the interface between the chip and the cap, thus increasing the thermal resistance of the interface. Pumping, or grease pumping as it is commonly referred, results as the gap between the chip and the cap increases and decreases, eventually forcing enough grease out of the gap, and forming a critical number of voids, to hinder thermal performance. This change in the gap thickness results as the substrate, to which the chip and cap are attached, and the cap bend to differing radii of curvature, due to the coefficient of thermal expansion (CTE) mismatch of the cap and substrate under thermomechanical loads. The stiff (nearly solid) nature of the grease contributes to the formation and coalescence of voids under this pumping action. A critical magnitude of tensile/compressive grease strain exists which results in maximum allowed thermal degradation. Another approach has been to attach a cap to the chip with an adhesive. This presents an opportunity to “balance” the package by matching the expansion and stiffness of the cap to that of the substrate so that the electronic package remains nearly flat at all temperatures. This approach is not, however, without problems. The CTE mismatch between the chip and the cap produces interfacial stresses between the adhesive and both the surface of the cap and the top surface of the chip. These stresses can cause delamination during the manufacturing process or during thermal cycling (chip operation in the field) near the corners and edges of the chip. Once delamination begins, crack propagation may ultimately lead to a defective product and/or electrical failure in the field. This is a major problem with capped chips particularly with flip chips on circuitized substrates of the organic type, such as epoxy laminate types.
The present invention is directed at overcoming the problems set forth above. It is desirable to have an electronic package and method to make the package that provides low thermal resistance, minimizes interfacial stresses, and is economical to manufacture. It is also desirable to have such an electronic package and method of manufacture that uses conventional assembly techniques. It is further desirable to have such an electronic package that does not require the presence of a thermally conductive grease between the chip and a thermally conducting member such as a cover or cap. Electronic packages produced by the method of this invention will have superior thermal performance and have much improved operational field life.
SUMMARY OF THE INVENTION
Accordingly, it is an object of this invention to enhance the art of packaging technology.
It is another object of this invention to provide a novel method for producing an electronic package that utilizes conventional assembly techniques to economically mass produce the package.
It is yet another object of this invention to provide an electronic package that minimizes interfacial stresses between the adhesive and both the chip and a cover or cap over the chip and results in much improved operational field life.
Still another object of this invention is to provide an electronic package that does not require the presence or use of thermal grease and has superior thermal performance.
According to one aspect of this invention, there is provided an electronic package, comprising a circuitized substrate having an upper surface, a semiconductor chip mounted on the upper surface of the circuitized substrate and electrically coupled to the substrate, the semiconductor chip having a substantially planar upper surface and at least one edge surface being substantially perpendicular to the substantially planar upper surface, the planar upper surface of the semiconductor chip having a defined area thereon. The electronic package further includes a thermally conductive member having upper and lower surfaces, the lower surface of the thermally conductive member being thermally coupled to the substantially planar upper surface of the semiconductor chip, the thermally conductive member further including at least one edge surface extending around a defined perimeter of the thermally conductive member. The thermally conductive member includes a body portion and a projecting portion, the body portion located substantially directly over the defined area of the planar upper surface of the semiconductor chip and having a bending stiffness greater than the bending stiffness of the projecting portion. The electronic package also includes a substantially rigid dielectric material positioned on at least a portion of the upper surface of the circuitized substrate and against at least a portion of the at least one edge surface of the thermally conductive member and against at least a portion of the at least one edge surface of the semiconductor chip.
According to another aspect of this invention, there is provided a method of making an electronic package comprising the steps of providing a circuitized substrate having an upper surface, mounting a semiconductor chip on the upper surface of the circuitized substrate, and electrically coupling the semiconductor chip to the circuitized substrate. The semiconductor chip has a substantially planar upper surface and at least one edge surface substantially perpendicular to the substantially planar upper surface, the planar upper surface of the semiconductor chip having a defined area thereon. A thermally conductive member is provided having upper and lower surfaces, at least one edge surface extending around a defined perimeter of the thermally conductive member, and further including a body portion and a projecting portion. The body portion of the thermally conductive member is positioned substantially directly over and in thermal communication with the defined area of the planar upper surface of the semiconductor chip, the body portion having a bending stiffness greater than the bending stiffness of the projecting portion. A dielectric material is also positioned on at least a portion of the upper surface of the circuitized substrate and against at least a portion of the at least one edge surface of the thermally conductive member and against at least a portion of the at least one edge surface of the semiconductor chip.
According to yet another aspect of the invention, there is provided a heat sink member comprising a body portion with a first bending stiffness and a first thickness, the body portion occupying a plane, and a projecting portion with a second bending stiffness and a second thickness, the projecting portion projecting from the body portion substantially within the plane, the body portion adapted for being thermally coupled to a defined planar area of a semiconductor chip, the first bending stiffness of the
Caletka David V.
Johnson Eric A.
Andujar Leonardo
Fischman Steven
Flynn Nathan J.
Fraley Laurence R.
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