Electronic memory device having bit lines with block...

Details Electronic memory device having bit lines with block... Electronic memory device having bit lines with block...

1999-08-31

2001-09-04

Chaudhari, Chandra (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S257000, C438S593000, C438S584000, C438S587000

Reexamination Certificate

active

06284585

ABSTRACT:

TECHNICAL FIELD
This invention relates to a memory block for implementing electronic memory devices integrated on a semiconductor and having cell matrices organized into sections, each section comprising at least one block.
The invention also relates to a process for manufacturing such blocks.
More particularly, the invention relates to an electronic memory device organized into sections which are in turn divided into blocks formed of cells and their associated decoding and addressing circuits, the cells being connected in a predetermined circuit configuration and each block being included between two opposite contact regions which are interconnected by parallel continuous conduction lines referred to as the bit lines.
The invention further concerns a method for manufacturing an integrated memory block, which block has a matrix-like configuration and is individually selectable from a plurality of blocks that make up a section and are embedded in a memory device.
BACKGROUND OF INVENTION
As is well known, electronic memory devices integrated on a semiconductor, whether of the EPROM or FLASH-EPROM type, are formed by cell matrices divided into ‘sections’. These sections are essentially sub-matrices comprising blocks of memory cells having predetermined dimensions.
Each block is provided with bias and address lines as required for identifying the individual memory cells and decoding the information contained therein.
A memory device of this kind is described, for example, in European Patent No. 0 573 728 to SGS-Thomson Microelectronics S.r.l.
This prior document discloses an integrated device of the EPROM or FLASH-EPROM type, wherein the individual blocks comprise a cell matrix made up of a plurality of word lines and bit lines lying orthogonally to one another. The intersections, of each word line with each bit line, define the memory cells.
A structure of this kind is known in the art as a cross-point matrix, and is distinctive in that the bit lines are formed on the semiconductor substrate by parallel continuous diffusion strips.
An innovative aspect of this particular configuration resides in the absence of metallization contacts from the substrate area intended for integration of the memory cells; this feature greatly enhances the capability for integration on semiconductor substrates.
Metal contacts are only provided at the opposite ends of the bit lines and represent “end” terminations of each memory block.
An electric diagram of this configuration is shown in the appended
FIG. 1
, where the presence of opposite contact regions
4
at the boundaries of the plural memory cells
3
can be seen.
Each memory cell
3
is delimited by a corresponding main continuous bit line
7
, and by a broken bit line also referred to as ‘segment’ of a bit line. Each segment is connected to an adjacent continuous bit line by an addressing active element
2
. There is one addressing, right or left, active element
2
for each bit line segment.
This circuit arrangement, as adopted for each of n-th memory blocks
1
, exhibits serious drawbacks whenever two or more blocks
1
are connected together in cascade to make up a section of the EPROM or FLASH-EPROM device, for example.
This connection, shown by way of example in
FIG. 2
, is provided by two contiguous memory blocks
1
sharing a region C(n) which incorporates the contacts
4
, and is the cause for undesired electrical continuity between all the continuous bit lines
7
belonging to the different blocks
1
.
Thus, so-called long bit lines are created as denoted by BLK, BLK+1, BLK+2 in FIG.
2
. The bias voltage for each bit line
7
is the same in each of the cascaded memory blocks.
This may have serious disadvantages during a drain-side writing operation into each memory cell
3
, since all of the remaining cells not involved in the writing, because belonging to two separate cascade connected n-th and (n−1)-th blocks, will find themselves in a potentially critical configuration known as ‘drain stress’.
In fact, the uninvolved cells in the writing may be subjected to a condition of no voltage on the corresponding word lines and of a high, about 5 or 6 Volts, voltage value on the bit line
7
.
This critical condition will be proportional to the number of cells sharing the same bit line
7
.
A simple calculation, as exemplified by the formula herein below, shows that the overall stress time t-stress is related to the time t-write required for writing each memory cell
3
, to the number_N cycles of the write cycles executed, and to the total number of word lines that intersect the biased bit line
7
for the write operation.
The last-mentioned term is obtained by multiplying the number n of cascaded memory blocks by the number m of the word lines included in each block.
A unity should be subtracted from the last-mentioned computed term to take account of the cell being written which is not subjected to a stress condition, as follows:
t-stress−tot=t_write*[(
n*m
)−1]*N_cycles
The value of t_stress thus obtained for a single block
1
is a high value due to the product of n*m; for a memory device having a higher density than 1 Mb, this value would be greater than 1000.
Another problem with long bit lines
7
resulting from the cascade connection of several memory blocks
1
is encountered during an erase operation.
During this step, in fact, the memory cells that share the same bit line are biased to a relatively high voltage value of 5 or 6 Volts, whereas a zero or negative potential is applied to the word lines that intersect that bit line.
Thus, the erase operation simultaneously affects all of the cells sharing the same bit line
7
biased to a high state.
It will be appreciated that the circuit scheme of the prior art does not allow the memory blocks
1
to be selected individually.
A possible solution for overcoming this limitation could be that of having a decode block arranged to interrupt the matrix structure at each memory block
1
.
While achieving its objective, such a solution would entail increased occupation of circuit area on the semiconductor substrate in order to accommodate the decode blocks.
Accordingly, an electrical scheme for the memory cells
3
would be desirable, wherein, while retaining the matrix configuration made up of elementary memory blocks, the individual blocks can be accessed independently even though connected together in cascade.
Another condition to be met is that the elementary memory block
1
should be compatible with conventional fabrication processes, such that its integration on the semiconductor substrate would involve no thorough re-designing of masks and process steps.
SUMMARY OF THE INVENTION
An object of this invention is to provide a novel circuit scheme and corresponding process for manufacturing memory blocks in a matrix type of layout, which have such constructional and functional features as to overcome the limitations and drawbacks of prior-art devices.
An embodiment of the present invention is directed to providing for controlled interruption of long bit lines by introducing a temporary electric discontinuity between cascade connected memory blocks.
The embodiment employs a memory block having at least one controlled switch arranged to act on each of the bit lines. Advantageously, the switch is placed near the region that accommodates the end contacts.
An embodiment of the present invention also provides a process for integrating an individually selectable memory block, which is compatible to a high degree with process flows conventionally used for making cell matrices.


REFERENCES:
patent: 5432730 (1995-07-01), Shubat et al.
patent: 5517448 (1996-05-01), Liu
patent: 5583808 (1996-12-01), Brahmbhatt
patent: 5590068 (1996-12-01), Bergemont
patent: 5761119 (1998-06-01), Asano
patent: 5790750 (1998-08-01), Nishizaki et al.
patent: 5822248 (1998-10-01), Satori et al.
patent: 5862076 (1999-01-01), Eitan
patent: 0580467A2 (1993-06-01), None
patent: 0 552 531 A1 (1993-07-01), None
patent: 0 580 467 A2 (1994-01-01), None
patent: WO 96/08824 (1996-03

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