Electronic discharge protective circuit for DRAM

Details Electronic discharge protective circuit for DRAM Electronic discharge protective circuit for DRAM

1998-11-06

2000-09-19

Nelms, David

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438238, 438275, 438210, 438253, 438302, 438396, H01L 218244

Patent

active

061210803

ABSTRACT:
A method of manufacturing an electrostatic discharge protective circuit for DRAM is disclosed. In the market, two gates are first formed on a substrate. A silicon oxide layer is formed over the substrate. Next, a contact window is formed in the silicon oxide layer to expose a common source/drain region between the two gates in the substrate and parts of the two gates. Since the two gates are formed at the same time, there is no problem with alignment accuracy in the formation of the contact window therebetween. Then, the contact window is filled by a conductive material, such as doped polysilicon, which is used to electrically connect the two gates and the common source/drain region.

REFERENCES:
patent: 5637187 (1997-06-01), Takasu
patent: 5843827 (1998-12-01), Gregor
patent: 5994176 (1999-11-01), Wu
patent: 5994755 (1999-11-01), Dejong et al.
patent: 6008081 (1999-11-01), Wu

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