Electronic device parameter estimator and method therefor

Details Electronic device parameter estimator and method therefor Electronic device parameter estimator and method therefor

2000-05-26

2002-06-11

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

Reexamination Certificate

active

06405349

ABSTRACT:

FIELD OF THE INVENTION
The current invention relates to the design of electronic devices. More specifically, the current invention relates to the design of electronic devices with components optimized for power consumption.
BACKGROUND OF THE INVENTION
In the design of electronic devices, e.g. integrated circuits, processors, and the like, power consumption and other parameters are significant to the design process. This is especially true when those devices are to be used in battery-powered or other equipment where power consumption is critical to operational life.
Utilizing a typical paradigm, the design of an integrated circuit passes through five levels: system, architecture, implementation, layout, and prototyping. At the system level, the designer conceives and designs the overall integrated circuit using a specific technology. At the architecture level, specific components of the integrated circuit required to realize the design, e.g. adders, RAMs, multipliers, etc., are selected from well-known building blocks peculiar to that specific technology. At the implementation level, interconnections between selected building blocks are defined to produce a homogenous circuit. At the layout level, the integrated circuit's physical topology is determined and masks are created from which the integrated circuit will be produced. Finally, at the prototype level a physical integrated circuit is produced.
Utilizing the paradigm discussed above as an example, the designer traditionally utilizes a probabilistic approach to determine power consumption and other design parameters at the system and architecture levels. That is, a composite of estimated gate count, rules of thumb, and experience-based “best guesses” are used to select components that the designer believes will fulfill the required function at the lowest power consumption.
At the layout level, conventional power analysis tools may be used to determine the probable power consumption of the integrated circuit as a whole and of each of the selected components. Verification of these probable power consumptions is performed through actual measurements of the prototype integrated circuit.
One disadvantage of this schema is its inaccuracy. Actual power consumption is often more than double that predicted by the designer during at the system and architecture level component selection. Also, since the actual power consumption is normally not discovered until the layout level, late in the design cycle, the implementation and layout design levels efforts would need to be scrapped and the designer return to the architecture level to select different components in order to make changes. This is often cost-prohibitive, resulting in undesirable compromises in the resultant integrated circuit.
What is needed is a method of accurately predicting power consumption and other design parameters at the architecture level, early in the design process, allowing the designer to objectively select the appropriate component for the task while reducing overall power consumption to a minimum.


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