Electronic device parameter estimator and method therefor

Details Electronic device parameter estimator and method therefor Electronic device parameter estimator and method therefor

1997-07-01

2000-07-18

Lintz, Paul R.

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

716 2, 716 18, 703 14, 703 18, G06F 1750

Patent

active

060901519

ABSTRACT:
A process (20) and design tool (62) are presented for the accurate prediction of design parameters (42) for components (38) of an integrated circuit (22) during the early stages of the design of that integrated circuit (22). These predicted design parameters (42) include pin count parameters (50), propagation delay parameters (52), layout area parameters (54), dynamic power parameters (56), static power parameters (58), and total power parameters (60). With these parameters, the designer interactively modifies the design prior to the layout and prototyping of the integrated circuit (22). The dynamic power parameters (56) and total power parameters (60) may be repetitively predicted with differing input items to establish a power usage pattern for the integrated circuit (22).

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Pant et al. ("Device-circuit Optimization For Minimal Energy And Power Consumption In Cmos Random Logic Networks", Proceedings of the 34th Design Automation Conference, Jun. 9, 1997, pp. 403-408).
Shen et al. ("CB-Power: a hierarchical cell-based power characterization and estimation environment for static CMOS circuits", Proceedings of the ASP-DAC '97, Asia and South Pacific Design Automation Conference, pp. 189-194, Jan. 1, 1997.
Tsui et al. ("Efficient estimation of dynamic power consumption under a real delay model", Proceeding of the 1993 IEEE/ACM International Conference on Computer-Aided Design, pp. 224-228, Jan. 1, 1993).
Borah et al. ("Transistor sizing for low power CMOS circuits", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 15, No. 6, pp. 665-671, Jun. 1, 1996).

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