Electronic digital logic circuitry – With test facilitating feature
Reexamination Certificate
2002-10-18
2004-05-25
Chang, Daniel D. (Department: 2819)
Electronic digital logic circuitry
With test facilitating feature
C326S093000, C710S058000
Reexamination Certificate
active
06741094
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an electronic apparatus test circuit to test PHY chips in conformity to IEEE 1394. More particularly, the invention relates to an electronic apparatus test circuit to test PHY chips in conformity to IEEE 1394, which can reduce testing time and cost without relying on a PLL circuit.
2. Description of the Related Art
FIG. 4
is a schematic that shows a related art electronic apparatus test circuit to test a PHY chip in conformity to IEEE 1394 of an electronic apparatus. In
FIG. 4
, the test circuit to test a PHY chip in conformity to IEEE 1394 of an electronic apparatus is equipped with a PLL (Phase-Locked Loop) circuit
47
that multiplies the frequency of a reference clock signal to a specified frequency, a divider circuit
49
that divides the multiplied frequency that is multiplied by the PLL circuit
47
to generate and output a system clock signal for a logic circuit and a clock signal for an encoder circuit, an input cell
41
that receives an input of data, a reception circuit
42
that receives data output from the input cell
41
, a decoder circuit
43
that decodes data received by the reception circuit
42
, a logic circuit
40
that processes with a specified logic circuit data decoded by the decoder circuit
43
according to the system clock signal for the logic circuit supplied from the divider circuit
49
, an encoder circuit
46
that encodes data processed by the logic circuit
40
according to the clock signal for the encoder circuit supplied from the divider circuit
49
, a transmission circuit
45
that transmits data encoded by the encoder circuit
46
, and an output cell
44
that outputs data provided from the transmission circuit
45
.
With this structure, when a PHY chip in conformity to IEEE 1394 is tested, a reference clock signal having a frequency of about 25 MHz is multiplied to about 400 MHz by the PLL circuit
47
, and the multiplied clock signal that has been multiplied by the PLL circuit
47
is divided by the divider circuit
49
to generate a system clock signal for the logic circuit having a frequency of about 50 MHz which is output to the logic circuit
40
, and to generate a clock signal for the encoder circuit having a frequency of about 400 MHz, about 200 MHz or about 100 MHz which is output to the encoder circuit
46
. Then, a test signal to test is input as data, and its output result is confirmed, whereby the PHY chip in conformity to IEEE 1394 is verified.
SUMMARY OF THE INVENTION
However, with the related art electronic apparatus test circuit, it takes about 50-100 microseconds from the moment when the power supply is turned on until an output signal (multiplied clock signal) from the PLL circuit
47
stabilizes, which is problematical because the test requires a long time.
Also, the characteristics of the internal clock signal that is supplied to the logic circuit
40
and the encoder circuit
46
are dependent on the precision of the PLL circuit
47
, which is an analog circuit. Therefore, depending upon the precision of the PLL circuit
47
, the apparatus may be judged as a defective product even when other component circuits, such as the logic circuit
40
, are normal, which results in the problem of high cost.
Accordingly, the present invention provides an electronic apparatus test circuit to test an I/O apparatus e.g. a PHY chip in conformity to IEEE 1394, which can reduce the testing time and cost without relying on a PLL circuit.
To address or solve the problems described above, an electronic apparatus test circuit in accordance with the present invention pertains to an electronic apparatus test circuit to test an I/O apparatus e.g. a PHY chip in conformity to IEEE 1394 of an electronic apparatus, which includes: a PLL (Phase-Locked Loop) circuit that multiplies a reference clock signal having a specified frequency; an external clock circuit that receives an input of a test signal, a multiplied clock signal that is multiplied to a specified frequency and output from the PLL circuit, and an external clock signal that is externally supplied and has a frequency identical with the specified frequency of the multiplied clock signal, and that outputs one of the multiplied clock signal and the external clock signal; and a divider circuit that divides the multiplied clock signal or the external clock signal output from the external clock circuit to generate and output a system clock signal for a logic circuit of the I/O apparatus and a clock signal for an encoder circuit of the I/O apparatus. The external clock circuit outputs the external clock signal when the test signal is ON.
The external clock circuit may include a first AND circuit that provides a logical product of the multiplied clock signal from the PLL circuit and an inverse signal of the test signal, a second AND circuit that provides a logical product of the external clock signal and the test signal, and an OR circuit that provides a logical sum of an output signal from the first AND circuit and an output signal from the second AND circuit, and outputs a clock signal having a frequency identical with the specified frequency of the multiplied clock signal.
The reference clock signal may preferably have a frequency of about 25 MHz, and the multiplied clock signal, the external clock signal and the test clock signal may preferably have a frequency of about 400 MHz, about 800 MHz, about 1600 MHz or about 3200 MHz.
The divider circuit may generate and output the system clock signal for the logic circuit having a frequency of about 50 MHz, and the clock signal for the encoder circuit having a frequency of about 3200 MHz, about 1600 MHz, about 800 MHz, about 400 MHz, about 200 MHz or about 100 MHz.
The divider circuit may generate and output the system clock signal for the logic circuit based on a speed code that is externally supplied. Also, the electronic apparatus test circuit is integrated in an I/O apparatus e.g. a PHY chip in conformity to IEEE 1394.
When the I/O apparatus is tested, since the external clock signal is used as a clock signal to provide testing, testing time and cost can be reduced without relying on a PLL circuit.
REFERENCES:
patent: 6202103 (2001-03-01), Vonbank et al.
patent: A 2001-289913 (2001-10-01), None
patent: 2002303656 (2002-10-01), None
Chang Daniel D.
Oliff & Berrige PLC
Seiko Epson Corporation
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