Electronic apparatus, silicon-on-insulator integrated...

Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Insulative material deposited upon semiconductive substrate

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C438S779000, C438S455000, C438S458000

Reexamination Certificate

active

07396779

ABSTRACT:
An electronic apparatus includes an insulative substrate containing an aluminum-based glass and a layer containing a semiconductive material over the substrate. The insulative substrate can include aluminum oxycarbide. The insulative substrate can exhibit a CTE sufficiently close to a CTE of the semiconductive material layer such that a strain of less than 1% would exist between a 1000 Angstroms thickness of the semiconductive material layer and the insulative substrate. The semiconductive material layer can include monocrystalline silicon. The electronic apparatus can be a silicon-on-insulator integrated circuit. An electronic apparatus fabrication method includes forming an insulative substrate containing an aluminum-based glass and forming a layer containing a semiconductive material over the substrate. Forming the insulative substrate can include forming a mixture of a powder containing aluminum, a powder containing silicon, and a powder containing carbon, reacting the mixture by spontaneous ignition, and forming the reacted mixture into a plate. Forming the semiconductive material layer can include removing a layer of silicon from a monocrystalline silicon wafer and bonding the silicon layer to the insulative substrate.

REFERENCES:
patent: 4241359 (1980-12-01), Izumi et al.
patent: 5234535 (1993-08-01), Beyer et al.
patent: 5441591 (1995-08-01), Forbes
patent: 5635429 (1997-06-01), Grogen et al.
patent: 6049106 (2000-04-01), Forbes
patent: 6093623 (2000-07-01), Forbes
patent: 6309950 (2001-10-01), Forbes
patent: 6924037 (2005-08-01), Joret et al.
patent: 2002/0135549 (2002-09-01), Kawata
patent: 2003/0010980 (2003-01-01), Yamazaki et al.
patent: 2005/0020094 (2005-01-01), Forbes et al.
C. Harendt et al. “Silicon on Insulator Material by Wafer Bonding,” J. Electronic Materials, vol. 20, No. 3, pp. 267-277, Mar. 1991.
S.M. Sze, Physics of Semiconductor Devices:, John Wiley & Sons, New York (1981), pp. 850-851.
J.B. Laksy, “Wafer Bonding for Silicon on Insulator Technologies,” Appl. Phys. Letters, vol. 48, No. 1, pp. 78-80, Jan. 1986.
M. Breul et al., “Smart-Cut: a New Silicon on Insulator Material Technology Based on Hydrogen Implantation and Wafer Bonding,” Proc. 1996 Int. Conf. On Solid State Devices and Materials, Japan. J. Appl. Phys., Part 1, vol. 36, No. 3B, pp. 1636-1641, 1996.
T. Suni et al, “Effects of Plasma Activation on Hydrophilic Bonding of Si and SiO2,” J. Electrochem. Soc., vol. 149, No. 6, pp. G348-51, Jun. 2002.
U.S. Appl. No. 10/443,335, filed May 21, 2003, Forbes.
S.S.K. Iyer et al., “Separation by Plasma Implantation of Oxygen (SPIMOX) operational phase space,” IEEE trans. On Plasma Science, vol. 25, No. 5, pp. 1128-1135, 1997.
G.A. Garcia et at, High Quality in Thin (100nm) Silicon on Sapphire, IEEE Trans Electron Devices vol. No. 9, No. 1, pp. 32-34, Jan. 1988.
E. Cartagena. G. Garcia, G. Imthurn, G. Kelley, H. Walker and L. Forbes, “Bonded Etchback Silicon on Sapphire Bipolar Junction Transistors,” Abstracts of ECS meeting, May 1993, Honolulu, Hawaii, p. 1199.
G.P. Imthurn, G.A. Garcia, H.W. Walker, and L. Forbes, “Bonded Silicon-On-Sapphire Wafers and Devices”, J. Appl. Phys., 72(6), Sep. 15, 1992, pp. 2526-2527.
P. Ball, “A Small Mountain of Materials Goes into Every Microchip,” Nature Science Update, Nov. 19, 2002, http://www.nature.com
su/-21028/021028-12.html.
“Materials Selector”, Reinhold Publishing Co., Penton/IPC. http://www.handyharmancanada.com/TheBrazingBook/comparis.htm, Dec. 2002.
Company page http://www.hithermaln.com/datasheets/index.cfm?page=values, Dec. 2002.
R. People et al, “Calculation of Critical Layer Thickness Versus Lattice Mismatch for GexSi1−x/Si Strained Layer Heterostructures,” Appl. Phys. Letters, vol. 47, p. 322-324, Aug. 1985.
R. People et al, “Erratum: Calculation of Critical Layer Thickness Versus Lattice Mismatch for GexSi1−x/Si Strained Layer Heterostructures,” Appl. Phys. Letters, vol. 49, p. 229, Jul. 1986.
G. Grenet et al., “Testing the Feasibility of Strain Relaxed Compliant Substrates,” Abstract of Electronic Materials Conference, Santa Barbara, Jun. 2002, p. 8.
K.D. Hobart et al, “High Ge-Content Relaxed Si1−xgexLayers by Relaxation on Compliant Substrate with Controlled Oxidation,” Abstract of Electronic Materials Conferences, Santa Barbara, Jun. 2002, pp. 8.
P. Moran et al., “Strain Relaxation in Wafer-bonded SiGe/Si Heterostructures Due to the Viscous Flow of an Underlying Borosilicate Glass,” Abstract of Electronic Materials Conference, Santa Barbara, Jun. 2002, pp. 8-9.
A.J. Auberton-Herve, “SOI: Materials to Systems,” Digest of the International Electron Device Meeting, San Francisco, Dec. 1996, pp. 5-10.
T. Tsuchida et al., “Self-combustion Reaction Induced by Mechanical Activation of Al-si-c Powder Mixtures,” European Journal of Solid State and Inorganic Chemistry (France), vol. 32, No. 7-8, pp. 629-638, 1995.
H.C. Yi, et al, “Combustion Synthesis of Aluminoborate Glass Matrices,” J. Mater. Synth. Process. (USA), vol. 8, No. 1, pp. 15-20, Jan. 2000.
Dip. -Ing, M. Wild, Dr. -Ing, A. Gillner, “Laser Assisted Bonding of Silicon and Glass in Micro-System Technology,” http://www/ilt.fhg.de/eng/jb00-s42.html, Jul. 2003.
Saman Dharmatilleke et al, “Anodic Bonding of Glass to Glass and Silicon to Glass or Silicon to Silicon Through a Very Thick Thermally Grown SiO2Layer,”Proceedings of IS 3M International Symposium on Smart Structures&Microsystems, Hong Kong, Oct. 19-21, 2000, p. 32. http://dolphin.eng.us.edu/projects/bonding/paper.pdf.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Electronic apparatus, silicon-on-insulator integrated... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Electronic apparatus, silicon-on-insulator integrated..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Electronic apparatus, silicon-on-insulator integrated... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2768362

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.