Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Patent
1995-06-06
2000-10-03
De Cady, Albert
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
G06F 1100
Patent
active
061287512
ABSTRACT:
An electronic apparatus includes a CPU, a ROM, a RAM, an input port, a data bus, an address bus, a patching portion address register and a patching interrupt vector register which are connected to the data bus. A comparator compares a coincidence of the address stored in the address register with an address on the address bus and, in response thereto, supplies an interrupt to an interrupt control portion of the CPU. The interrupt control portion of the CPU is also supplied with other interrupts, for other processing. Further, an external storage device, connected to the input port, supplies a program bug patching information to be stored into the RAM. The RAM includes a stack area in which, during interrupt processing, there are saved data written in the address register and the patching interrupt register. Thus, patching of program bugs can be carried out even during an interrupt.
REFERENCES:
patent: 4028678 (1977-06-01), Moran
patent: 4028679 (1977-06-01), Divine
patent: 4028683 (1977-06-01), Divine et al.
patent: 4028684 (1977-06-01), Divine et al.
patent: 4051460 (1977-09-01), Yamada et al.
patent: 4095278 (1978-06-01), Kihara
patent: 4150428 (1979-04-01), Inrig et al.
patent: 4218757 (1980-08-01), Drogichen
patent: 4291375 (1981-09-01), Wolf
patent: 4296470 (1981-10-01), Fairchild et al.
patent: 4319343 (1982-03-01), Powell
patent: 4400798 (1983-08-01), Francis et al.
patent: 4424574 (1984-01-01), Enoki et al.
patent: 4456966 (1984-06-01), Bringol et al.
patent: 4490783 (1984-12-01), McDonough et al.
patent: 4490812 (1984-12-01), Guterman
patent: 4517643 (1985-05-01), Bannai
patent: 4542453 (1985-09-01), Patrick et al.
patent: 4571677 (1986-02-01), Hirayama et al.
patent: 4610000 (1986-09-01), Lee
patent: 4620273 (1986-10-01), Mitani et al.
patent: 4709324 (1987-11-01), Kloker et al.
patent: 4727476 (1988-02-01), Rouchon
patent: 4745572 (1988-05-01), Wilburn
patent: 4751703 (1988-06-01), Picon et al.
patent: 4769767 (1988-09-01), Hilbrink
patent: 4802119 (1989-01-01), Heene et al.
patent: 4819154 (1989-04-01), Stiffler et al.
patent: 4831517 (1989-05-01), Crouse et al.
patent: 4905200 (1990-02-01), Pidsosny et al.
patent: 4942541 (1990-07-01), Hoel et al.
patent: 4972481 (1990-11-01), Santesson
patent: 5051897 (1991-09-01), Yamaguchi et al.
patent: 5063499 (1991-11-01), Garber
patent: 5199032 (1993-03-01), Sparks et al.
patent: 5214771 (1993-05-01), Clara et al.
patent: 5305460 (1994-04-01), Kaneko et al.
patent: 5408672 (1995-04-01), Miyazawa eyt al.
patent: 5454100 (1995-09-01), Sagane
patent: 5619678 (1997-04-01), Yamamoto
patent: 5623665 (1997-04-01), Shimada
patent: 5731972 (1998-03-01), Yamamoto
H. Trinh, "Short and Long ROS Patch", Technical Disclosure Bulletin, 24: (3) 1379-1382 (Aug. 1981).
Shimada, et al., "Program Patching of a ROM", U.S. Patent Application No. 07/882,268, FWC of U.S. Patent Application No. 08/368,758 filed May 13, 1992.
IBM Technical Disclosure Bulletin, vol. 31, No. 1, Jun. 1988, pp. 294-298.
Charlie Melear: "Applications for Microcomputers with E.sup.2 PROM." Electro/86 and Mini/Micro Northeast 11 (1986), Conference Record, Los Angeles, CA, USA, pp. 1/9, #12/2.
IBM Technical Disclosure Bulletin, vol. 26, No. 10B, Mar. 1984, New York, USA, pp. 5606/5607, L. Weiss: "Path microcode change level check."
IBM Technical Disclosure Bulletin, vol. 30, No. 5, Oct. 1987, "On-Site-ROS Patch Mechanism."
Patent Abstracts of Japan, vol. 7, No. 67 (P-184), Mar. 19, 1983 & JP-A-57 211 651 (Tokyo Shibaura Denki KK), Dec. 25, 1982.
Patent Abstracts of Japan, vol. 7, No. 90 (P-191), Apr. 14, 1983 & JP-A-58 016 350 (Tokyo Shibaura Denki KK), Jan. 31, 1983.
Patent Abstracts of Japan, vol. 14, No. 64 (P-1002), Feb. 6, 1990 & JP-A-01 286 029 (Sugawa Kazuyuki), Nov. 17, 1989.
Matsuno Katsumi
Yamamoto Iwao
Cady Albert De
Sony Corporation
Ton David
LandOfFree
Electronic apparatus and method for patching a fixed information does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Electronic apparatus and method for patching a fixed information, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Electronic apparatus and method for patching a fixed information will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-205919