Computer-aided design and analysis of circuits and semiconductor – Design of semiconductor mask or reticle – Layout generation
Reexamination Certificate
2011-06-07
2011-06-07
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Design of semiconductor mask or reticle
Layout generation
Reexamination Certificate
active
07958464
ABSTRACT:
A method for creating an electron beam pattern exposure, where a pattern of shapes is generated, including at least one of lines and vias. To each shape there is assigned a set of exposure pixels and edge placement constraints. An intensity at each exposure pixel is calculated by using a simplex method, and a latent resist image location is calculated by convolving a proximity function with the pixel intensities. A shape critical dimension and a shape edge slope is statistically evaluated by applying linear regression on the locations of the calculated latent image. The electron beam pattern exposures are produced using dosages linearly optimized on a rotated pixel grid to produce the shape critical dimension and the shape edge slope.
REFERENCES:
patent: 7106490 (2006-09-01), Sandstrom
patent: 7245352 (2007-07-01), Borodovsky et al.
patent: 2006/0141376 (2006-06-01), Levy et al.
Carroll Allen M.
Grella Luca
Bowers Brandon W
Chiang Jack
Kla-Tencor Corporation
Luedeka Neely & Graham P.C.
LandOfFree
Electron beam patterning does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Electron beam patterning, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Electron beam patterning will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2625893