Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
2002-03-28
2004-11-09
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S224000, C438S229000, C438S231000, C438S301000, C438S305000
Reexamination Certificate
active
06815358
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to lithography methods for printing and plating isolated narrow trenches with feature dimensions less than 100 nm, and more particularly, to a bi-layer lithographic method utilizing a thin undercoat dissolution layer beneath a resist layer.
BACKGROUND OF THE INVENTION
The areal density of magnetic disk storage has sustained annual increases of 100% during the last five years, largely due to shrinking dimensions in the read/write head. From a process perspective, this requires that the width of the critical read sensor and writer pole tip decrease by 20% to 30% each year. At 100 Gbit/in
2
density, assuming a 4 to 1 bit cell aspect ratio, a trackpitch should be approximately 160 nm. Considering approximately 20% for track misregistration (“TMR”), the trackwidth should be approximately 130 nm. Doubtlessly, with rapidly approaching high areal densities of 1 Terabit/in
2
, the critical dimension (“CD”) needs to be pushed down to 30 nm. Additionally, sufficient confinement of magnetic fields require the write pole tip to have an aspect ratio of between 7:1 to 10:1, which is achieved by electroplating high magnetic moment materials into a narrow trench printed in the resist. In the context of a narrow trench as described above, the aspect ratio is defined as the height divided by the width. The width is also referred to as the critical dimension, CD.
Accordingly, there is a need for a method for lithographic patterning of sub-100 nm isolated trench with a high aspect ratio and electroplating magnetic moment materials into the trench.
SUMMARY OF THE INVENTION
The invention provides a bi-layer lithography method for printing and plating sub-100 nm narrow trenches having a high aspect ratio. The method can include providing a thin layer of polymer as an undercoat dissolution layer disposed intermediate a substrate and a resist layer. The substrate can normally be coated with a non-magnetic seed layer prior to deposition of the undercoat layer. The resist and undercoat layer are exposed to a radiation source capable of sub-100 nm resolution, such as an electron beam, to pattern the narrow trench and an aqueous developer solution is then used to define the narrow trench. The exposed portions of the resist and undercoat dissolution layer are thereafter dissolved in a standard aqueous base developer solution to define the narrow trench. The narrow trench can then be electroplated with a high magnetic moment material to form, for example, a pole tip of a magnetic write head. Unlike the resist, the undercoat material can be more completely cleared off the seed layer by the developer solution. As a result, the sides of the narrow trench will be generally vertical, particularly at the base of the narrow trench, since relatively little of the undercoat material remains on the seed layer.
Additional steps can include one or more of the following: baking the undercoat layer after it has been deposited on the substrate/seed layer; baking the resist layer after it has been deposited on the undercoat layer; and baking both layers after e-beam exposure. The baking time and baking temperature can be calculated to control various properties of the process, particularly the dissolution rate of the undercoat layer.
Other details, objects, and advantages of the invention will become apparent from the following detailed description and the accompanying drawings of certain embodiments thereof.
REFERENCES:
patent: 4933743 (1990-06-01), Thomas et al.
patent: 5185294 (1993-02-01), Lam et al.
patent: 5360698 (1994-11-01), Hanrahan
patent: 5604073 (1997-02-01), Krounbi et al.
patent: 5670404 (1997-09-01), Dai
patent: 5786253 (1998-07-01), Hsu
patent: 5798559 (1998-08-01), Bothra et al.
patent: 5802700 (1998-09-01), Chen et al.
patent: 5828121 (1998-10-01), Lur et al.
patent: 5972570 (1999-10-01), Bruce et al.
patent: 6218056 (2001-04-01), Pinarbasi et al.
patent: 6303260 (2001-10-01), Hurditch et al.
patent: 6316360 (2001-11-01), Burton et al.
patent: 3635 462 (1987-04-01), None
patent: 0 543 158 (1993-05-01), None
patent: 0 651 433 (2000-07-01), None
Eckert Andrew Robert
Yang Xiaomin
Berry Renee R.
Buchanan & Ingersoll PC
Nelms David
Seagate Technology LLC
LandOfFree
Electron beam lithography method for plating sub-100 nm... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Electron beam lithography method for plating sub-100 nm..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Electron beam lithography method for plating sub-100 nm... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3279648