Electroless plated semiconductor vias and channels

Details Electroless plated semiconductor vias and channels Electroless plated semiconductor vias and channels

1999-10-12

2001-09-18

Picardat, Kevin M. (Department: 2823)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S622000, C438S624000, C438S627000

Reexamination Certificate

active

06291332

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to semiconductors and more specifically to electroless plating of conductors used in semiconductors.
BACKGROUND ART
In the manufacturing of integrated circuits, after the individual devices, such as the transistors, have been fabricated in the silicon substrate, they must be connected together to perform the desired circuit functions. This connection process is generally called “metallization”, and is performed using a number of different photolithographic and deposition techniques.
One metallization process, which is called the “damascene” technique, starts with the placement of a first channel dielectric layer, which is typically an oxide layer, over the semiconductor devices. A first damascene step photoresist is then placed over the oxide layer and is photolithographically processed to form the pattern of the first channels. An anisotropic oxide etch is then used to etch out the channel oxide layer to form the first channel openings. The damascene step photoresist is stripped and an adhesive layer is deposited to coat the walls of the first channel opening to ensure good adhesion and then a barrier layer to act as a barrier material to prevent diffusion of such conductive material into the oxide layer and the semiconductor devices. Depending upon the materials used, the adhesion layer may not be required so the combination of the adhesion and barrier material or the barrier material alone is collectively referred to as “barrier layer” herein. A seed layer is then deposited on the barrier layer to form a conductive material base, or “seed”, for subsequent deposition of conductive material. A conductive material is then deposited in the first channel openings and subjected to a chemical-mechanical polishing process, which removes the first conductive material above the first channel oxide layer and damascenes the conductive material in the first channel openings to form the first channels.
For multiple layers of channels, another metallization process, which is called the “dual damascene” technique, is used in which the channels and vias are formed at the same time. The via formation step of the dual damascene technique in one example starts with the deposition of a thin stop nitride over the first channels and the first channel oxide layer. Subsequently, a separating oxide layer is deposited on the stop nitride. This is followed by deposition of a thin via nitride. Then a via step photoresist is used in a photolithographic process to designate round via areas over the first channels.
A nitride etch is then used to etch out the round via areas in the via nitride. The via step photoresist is then removed, or stripped. A second channel dielectric layer, which is typically an oxide layer, is then deposited over the via nitride and the exposed oxide in the via area of the via nitride. A second damascene step photoresist is placed over the second channel oxide layer and is photolithographically processed to form the pattern of the second channels. An anisotropic oxide etch is then used to etch the second channel oxide layer to form the second channel openings and, during the same etching process to etch the via areas down to the thin stop nitride layer above the first channels to form the via openings. The damascene photoresist is then removed, and a nitride etch process removes the nitride above the first channels in the via areas. A barrier layer is then deposited to coat the via openings and the second channel openings. Next, a seed layer is deposited on the barrier layer. This is followed by an electroplating of the conductive material on the seed layer in the second channel openings and the via openings to form the second channel and the via. A second chemical-mechanical polishing process leaves the two vertically separated, horizontally perpendicular channels connected by a cylindrical via.
The use of the damascene techniques eliminates metal etch and dielectric gap fill steps typically used in the metallization process. The elimination of metal etch steps is important as the semiconductor industry moves from aluminum to other metallization materials which are very difficult to etch. Materials such as gold (Au), silver (Ag), nickel (Ni), palladium (Pd), and platinum (Pt) have been explored with copper (Cu) becoming replacement of choice due to low resistance and cost.
There are several methods for depositing copper, however, only two so far can successfully put copper into the small geometries of the channels and vias required for
CVD is too expensive in terms of the specialty (copper laced) gases used to solidify copper onto the wafer in a CVD reactor. It also returns a poor yield (more reverse than forward reaction). Unlike CVD, which is single wafer process, electroplating can be done in batches so it tends to be a less costly process.
Electroplating requires a seed layer to attract copper ions to grow in a certain orientation. A favored seed technique employs global deposition or sputtering of a thin layer of copper having a (111) crystal orientation onto the entire wafer surface, including the sidewalls and bottom of the channels and vias. The entire wafer then is submerged into a bath of ionic solution laced with copper. Electrodes are attached at the edges of wafer and a small potential is applied across the wafer. Using the copper seed layer on top of the wafer as cathode the potential causes attraction of the copper ions toward the wafer. By accepting two electrons from the cathode, the copper ions become solidified and attached to the copper seed layer.
After electroplating, the wafer contains a thick layer of copper and its topography is no longer planar. For the dual damascene technique, where copper is filled onto both channels and vias, the non-planarity is even worse. An aggressive chemical-mechanical polish (CMP) is required to remove all traces of the copper from the inactive region (where there are no channels or vias). The aggressive CMP can lead to non-uniformity, micro-scratches, and dishing of the wafer. It also leads to erosion in the dense pattern regions and dishing on the wide channels. Furthermore, previous layer dishing and erosion profiles propagate to later layers further exacerbating the dishing problems. Dishing in the wide channels also reduces the cross-sectional area of the channels, which leads to high resistance. Micro-scratches may trap copper particles in between channels and thus lead to short currents.
A method for selectively depositing conductive material only in the channels and vias of a semiconductor wafer in a batch mode has long been sought but eluded those skilled in the art. As the semiconductor industry is moving from aluminum to copper and other type of materials with greater electrical conductivity and thinner channels and vias, it is becoming more pressing that a solution be found.
DISCLOSURE OF THE INVENTION
The present invention provides a method for manufacturing a semiconductor device in which a semiconductor substrate with a dielectric layer has channel openings formed in the dielectric layer. A seed layer is formed over the dielectric layer and in the openings followed by a resist over the seed layer. The resist is then removed outside the openings. The seed layer outside the openings, which is not covered by the resist, is removed and the seed layer in the openings remains intact because of the resist in the openings. The resist inside the openings is removed and the seed layer inside the openings is electroless plated in a batch mode to fill the openings and form the channels for interconnecting the semiconductor device.
The present invention further provides a method for forming conductive layers in semiconductor vias by processing a seed layer covered wafer to leave the seed layer only in the channels and vias for electroless plating on the seed layer to form the channels and vias. The process involves coating the seed layer with a resist and stripping the resist from the surfaces of the wafer to leave the resist only in the channels and vias. A reverse p

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