Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2000-02-10
2002-05-28
Clark, Jhihan B (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S750000, C257S751000, C257S780000, C257S781000
Reexamination Certificate
active
06396148
ABSTRACT:
TECHNICAL FIELD
The present invention relates in general to fabricating chips first single or multichip packaging structures, and more particularly, to electroless metallization processes for making direct electrical connection to aluminum integrated circuit contact pads.
BACKGROUND OF THE INVENTION
“Chips first” packaging structures are discussed in detail in commonly assigned U.S. Pat. No. 5,841,193 by Charles W. Eichelberger entitled, “Single Chip Modules, Repairable Multichip Modules, and Methods of Fabrication Thereof,” the entirety of which is hereby incorporated herein by reference. The major approaches to chips first packaging (which are described therein) are the Advance Multichip Module (AMCM) approach, and the High Density Interconnect (HDI) approach, along with its offshoots including the Plastic Encapsulated MCM. In each of these structures, the chips are covered by a layer of polymer that contains via holes down to interconnection pads on the underlying integrated circuit (IC) chips. Metallization is applied and patterned to provide an interconnect layer on the polymer above the IC chips and also to provide connection to the bond pads of the IC chips themselves.
In most, if not all, prior approaches this metallization layer is provided by means of sputtering. Sputtering possesses three advantages. First, any oxide on the aluminum bond pad can be removed by back sputtering, then without breaking vacuum, the metallization can be applied. Second, because of the energy of the sputtering, cleaning of the back sputtering, and use of adhesion promoting thin metal layers, the adhesion of the metallization to the polymer surface is very good. Third, the sputtering process does not chemically attack aluminum bond pads. The major disadvantage of sputtering processing is that it is expensive. Sputtering must be done in a very clean chamber under high vacuum conditions. Energy for sputtering is provided by elaborate high voltage power supplies using magnetron sputtering heads that require water cooling. Elaborate transfer techniques must also be used to transfer the substrate between sputter cleaning operations and past the sputtering targets.
By comparison, most printed circuit processing uses electroless metallization in which metal is deposited on a polymer surface by an auto catalytic chemical reaction. A typical sputtering machine costing one million dollars can, e.g., do sixteen 5″×5″ panels in an hour. In contrast, an electroless printed circuit line costing one hundred thousand dollars can process more than 160 5″×5″ panels in an hour. This gives electroless metallization techniques a cost advantage of a factor of 100. The problem with using electroless processing stems from the fact that printed circuit metallization electroless processes are very aggressive toward aluminum bond pads of integrated circuit chips. For this reason, printed circuit electroless metallization processes have not been used to apply metal to chips first structures. The present invention is directed to solving this problem.
DISCLOSURE OF THE INVENTION
In view of the above, an object of the present invention is to provide an electronic interconnect and packaging structure in which both the interconnect metallization above the chips first integrated circuit chips and the connections to the integrated circuit chips are provided by electroless plating.
Another object of the invention is to provide a method for making electrical connection to integrated circuit bond pads using an electroless plating process that plates on both the polymer above the chips and on the metal bond pads, and that does not attack the bond pad.
A further object of the invention is to provide a method for fabricating an electronic packaging structure using electroless plating processes, where polymer conditioning and adhesion promotion processes, as well as the electroless metallization process itself, do not attack aluminum bond pads.
Briefly summarized, the invention comprises in one aspect an integrated circuit structure which includes at least one integrated circuit having at least one contact pad for electrically connecting thereto. An electroless barrier metal is disposed over and in electrical contact with the at least one contact pad of the integrated circuit. The electroless barrier metal comprises a first electroless metal which is a different material than the conductive material forming the at least one contact pad of the integrated circuit. An electroless interconnect metal is disposed above and electrically connected to the electroless barrier metal over the at least one contact pad to facilitate electric connection to the integrated circuit. The electroless interconnect metal comprises a second electroless metal, wherein the second electroless metal is different from the first electroless metal comprising the electroless barrier metal.
In another aspect, an integrated circuit structure is provided which includes at least one integrated circuit having multiple contact pads for electrically connecting thereto. The multiple contact pads include at least one aluminum contact pad and at least one non-aluminum contact pad. An electroless barrier is disposed over and in electrical contact with the at least one aluminum contact pad of the integrated circuit. The electroless barrier metal can comprise electroless nickel. An electroless interconnect metal is disposed above and electrically contacts the electroless barrier metal to facilitate electrical connection to the at least one aluminum contact pad of the integrated circuit, and is disposed above and electrically contacts the at least one non-aluminum contact pad of the integrated circuit. The electroless interconnect metal comprises an electroless material that is different from the electroless nickel comprising the electroless barrier metal.
In a further aspect, a method of fabricating an integrated circuit structure is provided. The method includes: providing at least one integrated circuit having at least one contact pad exposed on a surface thereof; employing electroless processing to form an electroless barrier metal over and in electrical contact with the at least one contact pad of the at least one integrated circuit, wherein the electroless barrier metal comprises a first electroless metal, the first electroless metal comprising a different material than a conductive material forming the at least one contact pad; and employing electroless processing to form an electroless interconnect metal above and electrically contacting the electroless barrier metal to facilitate electrical connection to the at least one contact pad of the at least one integrated circuit, wherein the electroless interconnect metal comprises a second electroless metal, the second electroless metal being different from the first electroless metal comprising the electroless barrier metal.
To restate, provided herein are processing techniques for depositing electroless metal in a chips first single chip or multichip packaging structure that allows direct electroless metallization to aluminum integrated circuit contact pads, while at the same time providing a strongly adhering metal on the surface of the polymer which overlies the integrated circuit chips. Advantageously, the electroless processes described herein are more cost effective than conventional sputtering techniques. In addition, electroless interconnect as described herein allows for enhanced interconnect redistribution, stress relief and the ability to use larger solder balls and wider interconnect spacing. Also, the processes described can be performed directly on the wafer, thereby eliminating the alternative process of chip placement, filler application, lapping and transfer.
REFERENCES:
patent: 5646068 (1997-07-01), Wilson et al.
patent: 5841193 (1998-11-01), Eichelberger et al.
patent: 6111317 (2000-08-01), Okada et al.
patent: 6187680 (2001-02-01), Costrini et al.
“EPIC CSP Assembly and Reliability Methods,” James E. Kohl et al., originally published in the Proceedings of CS198, San
Eichelberger Charles W.
Kohl James E.
Rickley Michael E.
Clark Jhihan B
EPIC Technologies, Inc.
Heslin Rothenberg Farley & & Mesiti P.C.
Radigan, Esq. Kevin P.
LandOfFree
Electroless metal connection structures and methods does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Electroless metal connection structures and methods, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Electroless metal connection structures and methods will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2848132