Electroless copper fill process

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C438S680000, C438S700000, C257SE21170, C257SE21174, C257SE21548, C257SE21549

Reexamination Certificate

active

07456102

ABSTRACT:
Disclosed is a procedure for bottom-up fill of electroless copper film in sub-micron integrated circuit features. By repeatedly placing an integrated circuit wafer in an electroless bath, a transient period of time of accelerated growth in the feature is repeated to achieve many small layers of deposition, each of which is thicker near the base of the feature. The net result is filing of the feature from the bottom-up fill without formation of voids. The electroless bath employed to form the continuous electroless copper film may include a reducing agent, a complexing agent, a source of copper ions, a pH adjuster, and optionally one or more surfactants and/or stabilizers.

REFERENCES:
patent: 4152467 (1979-05-01), Alpaugh et al.
patent: 5151168 (1992-09-01), Gilton et al.
patent: 5576052 (1996-11-01), Arledge et al.
patent: 5674787 (1997-10-01), Zhao et al.
patent: 5824599 (1998-10-01), Schacham-Diamand et al.
patent: 5891513 (1999-04-01), Dubin et al.
patent: 5913147 (1999-06-01), Dubin et al.
patent: 5969422 (1999-10-01), Ting et al.
patent: 5972192 (1999-10-01), Dubin et al.
patent: 6024857 (2000-02-01), Reid
patent: 6065424 (2000-05-01), Shacham-Diamand et al.
patent: 6136707 (2000-10-01), Cohen
patent: 6197181 (2001-03-01), Chen
patent: 6214193 (2001-04-01), Reid et al.
patent: 6284121 (2001-09-01), Reid
patent: 6527920 (2003-03-01), Mayer et al.
patent: 6551487 (2003-04-01), Reid et al.
patent: 6664122 (2003-12-01), Andryuschenko et al.
patent: 6716334 (2004-04-01), Reid et al.
patent: 99/47731 (1999-09-01), None
Andryuschenko et al., “Electroless and Electrolytic Seed Repair Effects on Damascene Feature Fill,” Proceedings of International Interconnect Tech. Conf., San Francisco Ca., Jun. 4-6, 2001, pp. 33-35.
Chen et al., “EDC Seed Layer for Inlaid Copper Metallisation,” Semiconductor Fabtech—12thEdition, 5 Pages, Jul. 2000.
Ken M. Takahashi, “Electroplating Copper into Resistive Barrier Films,” Journal of the Electrochemical Society, 147 (4) 1417-1417 (2000).
T.P. Moffat et al., “Superconformal Electrodeposition of Copper in 500-90 nm Features,” Journal of the Electrochemcial Society, 147 (12) 4524-4535 (2000).
Ritzdorf et al., “Electrochemically Deposited Copper,” Conference Proceedings ULSI XV 2000, Materials Research Society, 101-107.
Reid et al., “Optimization of Damascene Feature Fill for Copper Electroplating Process,” Shipley Company, IITC 1999, 3 Pages.
Reid et al., “Copper PVD and Electroplating,” Solid State Technology, Jul. 2000, www.solid-state.com, 86-103.
Reid et al., “Factors Influencing Fill of IC Features Using Electroplated Copper,” Adv Met Conf Proc 1999, MRS 10 Pages, (2000).
Shacham-Diamond et al., “Copper Electroless Deposition Technology for Ultr-Large-Scale-Integration (ULSI) Metallization,” Microelectronic Engineering 33 (1997) 47-58.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Electroless copper fill process does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Electroless copper fill process, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Electroless copper fill process will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4021181

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.