Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Configuration or pattern of bonds
Patent
1999-03-09
2000-10-24
Saadat, Mahshid
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Configuration or pattern of bonds
257693, 257737, 257738, 257778, 257783, 257779, 257735, H01L 2348, H01L 2352, H01L 2940
Patent
active
061371858
ABSTRACT:
An electrode structure as well as the fabrication method thereof is disclosed which may enable successful pad layout conversion of interconnection electrode pads on the periphery of an associated IC chip to a grid array of rows and columns of terminal solder pads arranged occupying the entire area of the opposite surface of the chip while permitting use of a minimized length of wire leads for interconnection therebetween. This is achieved by (i) preparing a flat square IC chip which has an array of regularly spaced peripheral bonding pads the number of which along each of four chip sides is equally defined by a function of 2i(2i-1) where "i" is an integer and which also has external connection pads made of aluminum, (ii) sequentially forming nickel and gold coat films on the chip by electroless plating techniques, (iii) electrically coupling by metal contacts using thermal compression-bonding techniques the peripheral bonding pads to the pad layout conversion substrate for rearrangement of the peripheral bonding pads into the grid array of solder pads, and (iv) filling an adhesion resin between the conversion substrate and the IC chip.
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Ishino Masakazu
Mita Mamoru
Satoh Ryohei
Clark Jhihan B.
Hitachi , Ltd.
Saadat Mahshid
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